No teaching, no narrative — just the terse, scannable facts you look up mid-interview-prep to jog your memory.
Looking for something else? Study Notes have more explanation per point. Guides are the full reference these are condensed from.
Minimum time data must be stable before the clock edge for it to be captured correctly.
Minimum time data must remain stable after the clock edge.
Required time minus arrival time. Positive = met; negative = violation.
Difference in clock arrival time at two different registers.
Drives sequence items onto the DUT interface.
Passively observes DUT signals and converts them into transactions.
Arbitrates and forwards sequence items from sequences to the driver.
Checks actual DUT behavior against expected behavior.
Conducts when gate is HIGH — used in the pull-down network.
Conducts when gate is LOW — used in the pull-up network.
Parasitic thyristor effect causing a short between VDD and GND — prevented with guard rings.
Output depends only on current state. More stable, one cycle slower to react.
Output depends on state + input. Faster reaction, can glitch.