VLSI Cheat Sheets: Timing, SDC, Verilog, UVM, CDC, DFT

Timing equations

TIMING

Setup (no skew): T_clk ≥ T_clk→q + T_logic,max + T_setup
Hold (no skew): T_clk→q + T_logic,min ≥ T_hold
With skew (capture − launch): Setup gains +skew. Hold needs +skew more margin.
Slack: Required time − arrival time (negative = violation)
Max frequency: f_max = 1 / (T_clk→q + T_logic + T_setup)
Clock period ↔ frequency: 1 GHz = 1 ns · 500 MHz = 2 ns · 100 MHz = 10 ns
Synchronizer MTBF: e^t_r/τ / (T_w · f_clk · f_data)
Multicycle N (setup): Setup checked N cycles later, so hold usually needs −hold N−1

STA terms

TIMING

WNS / TNS: Worst negative slack / total negative slack over all failing endpoints
Skew: Difference in clock arrival between launch and capture flops
Jitter: Cycle-to-cycle variation of the clock edge. Modelled as uncertainty.
Latency (insertion delay): Delay from the clock source to a flop's clock pin
OCV / AOCV / POCV: On-chip variation derates: flat / depth-based / statistical
CRPR: Removes pessimism on the clock path shared by launch and capture
False path: Never exercised functionally, so excluded from timing
Recovery / removal: Setup/hold-like checks for asynchronous reset release
Time borrowing: A latch-based path using time from the next stage

SDC commands you'll actually use

TIMING

create_clock -name clk -period 10 [get_ports clk]: 100 MHz clock on port clk
create_generated_clock -divide_by 2 -source ...: A derived clock (divider, mux)
set_clock_uncertainty 0.1 [get_clocks clk]: Guard band for jitter (and skew pre-CTS)
set_input_delay 3 -clock clk [get_ports din]: External logic uses 3 ns of the cycle before the input
set_output_delay 2 -clock clk [get_ports dout]: External logic needs 2 ns after the output
set_false_path -from A -to B: Don't time this path
set_multicycle_path 2 -setup -from A -to B: Allow 2 cycles (pair with a -hold 1)
set_clock_groups -asynchronous -group c1 -group c2: Clocks with no phase relationship
set_max_transition 0.2 [current_design]: Design-rule limit on slew

Verilog operators and syntax

RTL

Bitwise: & | ^ ~ ~^ (operate on each bit)
Reduction: &a |a ^a (whole vector to 1 bit; ^a = parity)
Logical: && || ! (result is 1-bit true/false)
Equality: == != can give X. === !== compare X/Z literally.
Shift: << >> logical. <<< >>> arithmetic (sign-preserving).
Concatenate / replicate: {a, b} {4{1'b1}} = 4'b1111
Part-select: v[7:4], indexed v[i*8 +: 8]
Number literal: 8'hFF 4'b10x1 '0 fills with zeros (SV)
case variants: casez: z/? are don't-care. casex: also x (avoid).
Generate: genvar i; for (...) begin : g ... end for replicated hardware

RTL coding rules

RTL

Clocked blocks: always_ff + <=
Combinational blocks: always_comb + = + default values at the top
Never: Mix = and <= in one block. Drive one signal from two blocks.
Latches: Come from incomplete if/case in combinational code
Clocks: Use enables or library ICG cells. Never gate with logic.
Reset: Async assert, sync release. One synchronizer per clock domain.
FSM: Named states, default next state, and a register for glitch-free outputs if needed
Widths: Size every constant and operand. Watch implicit 32-bit math.

SystemVerilog types and containers

VERIFICATION

4-state: logic, reg, integer, wire (net)
2-state: bit, byte (8, signed), shortint, int (32, signed), longint
Dynamic array: int d[]; d = new[n];
Queue: int q[$]; q.push_back(x); q.pop_front();
Associative: int m[string]; m.exists(k); m.delete(k);
Struct / enum: typedef struct packed {...} t; enum {IDLE, RUN} s;
Class handle: pkt p = new(); Copying a handle doesn't copy the object.

Randomization and constraints

VERIFICATION

rand / randc: Any legal value / cycles through all values before repeating
Range: x inside {[1:10], 20};
Weights: x dist {0 := 1, [1:9] :/ 9}; (:= per value, :/ shared)
Implication: mode == BURST -> len > 1;
Ordering: solve a before b; (changes the distribution, not legality)
Soft: soft len == 4; (can be overridden without a conflict)
Inline: assert(p.randomize() with { addr < 16; });
Control: p.c_len.constraint_mode(0); p.len.rand_mode(0);

SVA operators

VERIFICATION

a |-> b: If a, check b in the same cycle
a |=> b: If a, check b in the next cycle
##n, ##[m:n]: Delay n cycles / between m and n cycles
[*n]: Consecutive repetition, e.g. busy[*3]
$rose $fell $stable $past: Edge and history functions
disable iff (!rst_n): Turn the check off during reset
assert / cover / assume: Check / prove it happens / constrain formal inputs

UVM at a glance

VERIFICATION

Components: test → env → agent (sequencer, driver, monitor) + scoreboard
Objects: sequence items, sequences, config objects
Phase order: build ↓ · connect ↑ · end_of_elaboration · start_of_simulation · run · extract · check · report · final
Create: x = my_t::type_id::create("x", this);
Config: uvm_config_db#(T)::set(ctx, path, name, val) / ::get(...)
Stimulus: start_item → randomize → finish_item ↔ get_next_item → drive → item_done
End of test: phase.raise_objection(this) ... drop_objection(this)
Plusargs: +UVM_TESTNAME, +UVM_VERBOSITY, +UVM_OBJECTION_TRACE

CMOS and power

CIRCUITS

NMOS: Conducts when gate = 1. Pull-down network, passes a strong 0.
PMOS: Conducts when gate = 0. Pull-up network, passes a strong 1.
NAND vs NOR: NAND is faster (series NMOS). NOR stacks slow PMOS in series.
PMOS sizing: About 2–3× wider than NMOS for equal rise and fall
Dynamic power: P = α · C · V² · f
Leakage: Subthreshold + gate + junction. Grows with temperature.
Latch-up: Parasitic PNPN turns on. Prevented by well taps and guard rings.
Low-power knobs: Clock gating (α) · DVFS (V, f) · power gating and multi-Vt (leakage)

CDC decision table

CLOCKING

1-bit level, slow → fast: 2-flop synchronizer
1-bit pulse, fast → slow: Toggle + synchronizer + edge detect (pulse synchronizer)
Multi-bit, occasional: Req/ack handshake with the data held stable
Multi-bit, streaming: Async FIFO with Gray-coded pointers
Counter / pointer: Gray code, then synchronize
Reset: Reset synchronizer per domain
Never: Per-bit synchronizers on a bus, logic before a synchronizer, reconvergence

DFT terms

TEST

Scan chain: Flops linked as a shift register in test mode
Shift / capture: Load a pattern / clock the logic once / unload the result
Stuck-at: A node fixed at 0 or 1. The baseline fault model.
Transition: Slow-to-rise or slow-to-fall. Needs at-speed test.
LOC / LOS: Launch-on-capture / launch-on-shift (at-speed methods)
ATPG: Automatic test pattern generation
Coverage: Fault coverage = detected ÷ total faults
MBIST / LBIST: Built-in self-test for memories / logic
JTAG: IEEE 1149.1 boundary scan and test access port

Physical design files

PHYSICAL DESIGN

Netlist (.v): Gate-level connectivity from synthesis
SDC: Timing constraints
LEF: Abstract physical view of cells and macros, and technology rules
.lib / .db: Cell timing, power and function at a corner
DEF: Placed and routed design data exchanged between tools
SPEF: Extracted parasitics (R and C) for STA
SDF: Back-annotated delays for gate-level simulation
UPF: Power intent: domains, supplies, isolation, retention
GDSII / OASIS: Final layout for the foundry

VLSI cheat sheets: the facts you look up, on one page

Timing equations

STA terms

SDC commands you'll actually use

Verilog operators and syntax

RTL coding rules

SystemVerilog types and containers

Randomization and constraints

SVA operators

UVM at a glance

CMOS and power

CDC decision table

DFT terms

Physical design files

PDF cheat sheets

RTL Design Essentials

Verilog Essentials

VLSI Career Roadmap