CLOCK DOMAIN CROSSING INTERVIEW PREP

580 CDC questions. Every one answered.

Metastability to reset domain crossing in 27 chapters. Every answer is written the way you'd say it in an interview, with a tip for the follow-up. Includes 20 coding exercises with solutions, 25 solved numericals and 30 debugging scenarios.

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550+ Clock Domain Crossing (CDC) Interview Questions ebook cover — VLSI Beginners
580
QUESTIONS, ALL ANSWERED
20
CODING EXERCISES
25
SOLVED NUMERICALS
30
DEBUG SCENARIOS
THE PROBLEM

CDC bugs pass simulation and fail in silicon

That's exactly why interviewers dig into it. A missing synchronizer, a bus synchronized bit by bit, or a reset released in the wrong domain won't show up in a normal RTL simulation. It shows up as a rare hang in the lab, or in the field at high temperature.

Most candidates stop at "use two flops". Interviews go further: why MTBF is exponential in resolution time, why Gray pointers still need a max-delay, how async FIFO flags are computed, what reconvergence is, how resets cross domains, and how you'd prove a design is CDC-clean.

This book follows the order you'd learn CDC on a real project: single-bit crossings first, then multi-bit schemes and FIFOs, then resets, constraints and implementation, then verification and real systems, and finally the interview itself.

WHAT'S INSIDE

More than a question list

CDC interviews test four skills: explaining a crossing, writing the RTL, working out the numbers and debugging a failure. The book trains each one.

CONCEPTS

An answer and a tip for every question

Each of the 580 questions has a difficulty level, an interview-ready answer, and an Interview Tip: the follow-up question or common mistake the interviewer is listening for.

CODING

20 CDC coding exercises

Two-flop and reset synchronizers, toggle synchronizers, pulse stretchers, safe edge detectors, handshakes, Gray converters, async FIFO pointers and flags, and glitch-free clock muxes.

NUMERICALS

25 solved problems, step by step

MTBF and the gain from an extra stage, system MTBF, synchronizer latency, pulse widths, handshake throughput, FIFO depth, Gray conversion, max-delay values and ppm drift.

FIGURES

Diagrams you can redraw

The metastability waveform, the synchronizer chain, handshakes, the async FIFO with Gray pointers, and an annotated CDC tool report walked through line by line.

SIGNOFF

Where senior rounds go

Reconvergence, reset domain crossing, set_max_delay -datapath_only, synthesis and placement hazards, CDC-aware simulation, metastability injection, formal, and low-power crossings.

REVISION KIT

Built for the night before

A formula sheet, a technique selection guide, a 30-question rapid-fire round, a glossary, a 7-day plan and a readiness checklist.

LOOK INSIDE

Read twelve real pages before you buy

These are pages from the actual PDF, not mockups. Click any page to zoom in and read it in full.

Table of contents showing 27 chapters in five parts and four appendices, totalling 580 questions
PAGE 5Contents: all 27 chapters
Chapter 2 opener with the MTBF formula box and a waveform showing a flop going metastable and resolving
CHAPTER 2Metastability, with waveform
Chapter 3 page on virtual clocks, same-frequency clocks, skew between related clocks and clock-domain islands
CHAPTER 3Clock relationships
Chapter 6 opener on why buses can't be synchronized bit by bit and the principle behind safe multi-bit schemes
CHAPTER 6The multi-bit problem
Chapter 9 page on non-power-of-two FIFOs, bus skew, Johnson counters and crossing binary counters
CHAPTER 9Gray code and counters
Chapter 11 page on FIFO sizing with clock tolerance, verifying depth, elastic buffers, ppm drift and underflow
CHAPTER 11FIFO depth and elastic buffers
Chapter 16 opener on how synthesis breaks synchronizers, placement, dedicated synchronizer cells and clock skew
CHAPTER 16CDC through synthesis and P&R
Chapter 19 page on CDC-aware gate-level simulation, verifying async FIFOs, CDC coverage and reset testing
CHAPTER 19CDC-aware simulation
Chapter 21 page on gated destination clocks, wake-up signals, retention, power-gating handshakes and Q-channel
CHAPTER 21Low-power crossings
Chapter 23 page with SystemVerilog solutions for async FIFO pointer synchronizers, a safe edge detector and a pulse stretcher
CHAPTER 23Coding exercises
Chapter 25 opener with scenarios on field hangs at high temperature, async FIFO corruption on FPGA and bit-by-bit bus waivers
CHAPTER 25Debugging scenarios
Chapter 26 page of one-line rapid-fire answers on FIFO flags, pulses, reconvergence, resets and constraints
CHAPTER 26Rapid-fire round
HOW IT'S STRUCTURED

Five parts, from one flop to a whole SoC

The chapters build the way CDC is learned on a real project: single-bit crossings, then multi-bit schemes and FIFOs, then resets, constraints and implementation, then verification and real systems, and finally the interview itself.

PART I — FUNDAMENTALS & SINGLE-BIT CROSSINGS
What every CDC question builds on
CH 1–5CDC fundamentals, metastability and MTBF, clock relationships and domains, single-bit synchronizers, pulse and event synchronization
114QUESTIONS
PART II — MULTI-BIT CROSSINGS & FIFOS
Where most real CDC bugs live
CH 6–12Multi-bit problems and principles, handshake synchronizers, MUX-recirculation and enable-based capture, Gray code and counters, async FIFO design, FIFO depth and rate matching, reconvergence and divergence
140QUESTIONS
PART III — RESETS, CONSTRAINTS & IMPLEMENTATION
Keeping a correct design correct
CH 13–17Reset design and reset synchronizers, reset domain crossing (RDC), CDC timing constraints and STA, CDC in synthesis and physical design, clock gating, muxing and glitch-free switching
106QUESTIONS
PART IV — VERIFICATION & REAL SYSTEMS
What separates juniors from seniors
CH 18–24Structural CDC analysis and tools, simulation, metastability injection and formal, CDC in FPGAs, low-power and multi-voltage CDC, buses, interrupts, registers and counters, 20 coding exercises, 25 solved numericals
145QUESTIONS
PART V — INTERVIEW PRACTICE
Rehearsing the real thing
CH 25–2730 scenario-based debugging and design questions, a 30-question rapid-fire round, and interview strategy for CDC-focused roles
75QUESTIONS
TOTAL ACROSS 27 CHAPTERS + 4 APPENDICES 580 questions
DIFFICULTY SPLIT
120 Beginner: fundamentals every candidate must know407 Intermediate: expected with project exposure53 Advanced: architecture and signoff depth
SEE ALL 27 CHAPTERS
#CHAPTERQUESTIONS
PART I · FUNDAMENTALS AND SINGLE-BIT CROSSINGS
01CDC FundamentalsQ1–Q25
02Metastability and MTBFQ26–Q50
03Clock Relationships and Clock DomainsQ51–Q70
04Single-Bit SynchronizersQ71–Q95
05Pulse and Event SynchronizationQ96–Q114
PART II · MULTI-BIT CROSSINGS AND FIFOS
06Multi-Bit CDC: Problems and PrinciplesQ115–Q134
07Handshake SynchronizersQ135–Q154
08MUX-Recirculation, Enable-Based Capture and Data HoldingQ155–Q169
09Gray Code and Counter CrossingsQ170–Q189
10Asynchronous FIFO DesignQ190–Q214
11FIFO Depth Calculation and Rate MatchingQ215–Q234
12Reconvergence and DivergenceQ235–Q254
PART III · RESETS, CONSTRAINTS AND IMPLEMENTATION
13Reset Design and Reset SynchronizersQ255–Q279
14Reset Domain Crossing (RDC)Q280–Q300
15CDC Timing Constraints and STAQ301–Q325
16CDC in Synthesis and Physical DesignQ326–Q340
17Clock Gating, Clock Muxing and Glitch-Free Clock SwitchingQ341–Q360
PART IV · VERIFICATION AND REAL SYSTEMS
18CDC Verification: Structural Analysis and ToolsQ361–Q385
19CDC Verification: Simulation, Metastability Injection and FormalQ386–Q405
20CDC in FPGAsQ406–Q425
21Low-Power and Multi-Voltage CDCQ426–Q440
22CDC in Real Systems: Buses, Interrupts, Registers and CountersQ441–Q460
23CDC Coding Exercises with SolutionsQ461–Q480
24Numerical Problems with Step-by-Step SolutionsQ481–Q505
PART V · INTERVIEW PRACTICE
25Scenario-Based Debugging and Design QuestionsQ506–Q535
26Rapid-Fire Revision RoundQ536–Q565
27Interview Strategy for CDC-Focused RolesQ566–Q580
APPENDICES
ACDC Technique Selection Guidep. 148
BGlossary of CDC Termsp. 149
CFinal Interview Readiness Checklistp. 151
DA Final Wordp. 152
FROM THE BOOK

Five real questions, as printed

A classic trick question, the multi-bit principle, a constraints question, a coding exercise and an FPGA debugging scenario. Every question in the book has the same parts: a direct answer and an interview tip.

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Q66BEGINNER Is a crossing between two clocks of the same frequency safe without a synchronizer? Only if they come from the same source with known phase, so STA times the path. Two independent 100 MHz oscillators are asynchronous despite equal frequency: their phase drifts, so a synchronizer is required. Tip: "Same frequency is not the same clock" is a classic trick question.
Q116BEGINNER What is the fundamental principle of safe multi-bit CDC? Either ensure only one bit changes at a time (Gray coding), or hold the data stable in the source while a single-bit control signal is synchronized to say it can be captured (handshake, MUX-enable, FIFO). The data itself is never synchronized bit by bit. Tip: "Synchronize one control bit, hold the data still" is the universal recipe.
Q179INTERMEDIATE · CONSTRAINTS What is bus skew and how does it threaten Gray-coded crossings? If routing delays of different Gray bits differ by more than about one destination period, two single-bit changes can arrive together, so two bits appear to change between samples. Constraining the max delay of Gray bits to under one destination period prevents it. Tip: Mention set_max_delay -datapath_only on each pointer bit as the standard constraint.
Q472INTERMEDIATE · CODING Write an edge detector that is safe for an asynchronous input. Synchronize first with two ASYNC_REG flops, keep a delayed copy of the synchronized output, then rise = s[1] & ~s_d. Edges are detected only on the synchronized signal and its delayed copy. Tip: A common bug is edge-detecting the first synchronizer stage. Explain why it's wrong.
Q507INTERMEDIATE · SCENARIO Simulation passes, but an FPGA prototype occasionally shows corrupted data from an async FIFO. What do you check? Gray pointers registered in the source domain; pointer synchronizers with ASYNC_REG placed adjacent; max-delay constraints on pointer crossings not overridden by clock groups; correct full/empty logic; consistent reset on both sides; and no ignored overflow. Then use an ILA on flags and pointers. Tip: Missing max-delay on pointers is a frequent FPGA root cause.
INTERVIEW IN A WEEK?

The 7-day revision plan from the book

Answer each question aloud before reading the answer. Draw the synchronizer, the four-phase handshake and the async FIFO from memory until you can do it in two minutes, and solve every Chapter 24 numerical on paper.

DAY 1Ch 1–4Fundamentals, metastability and MTBF, clock relationships, two-flop synchronizer
DAY 2Ch 5–8Pulse crossings, the multi-bit problem, handshakes, MUX-enable
DAY 3Ch 9–11Gray code, draw the async FIFO, FIFO depth problems
DAY 4Ch 12–14Reconvergence, reset synchronizers, RDC
DAY 5Ch 15–19Constraints, implementation, clock muxing, verification
DAY 6Ch 20–24FPGA, low power, real systems, coding, numericals
DAY 7Ch 25–27Scenarios, rapid-fire, strategy, formula sheet
WHO THIS IS FOR

Useful wherever you're starting from

Students and freshers

CDC shows up in almost every RTL and verification interview. Parts I and II give you the answers freshers are expected to know cold.

RTL and SoC designers

Designing interfaces between blocks, clocks and power domains: handshakes, FIFOs, reset synchronizers, RDC and clock switching.

Verification and FPGA engineers

Running CDC tools, writing waivers, metastability injection, CDC-aware simulation, and FPGA-specific constraints and debug.

Self-learners

Studying without a mentor? Every question is answered and every coding exercise has a solution, so you can check your own reasoning.

550+ FPGA Interview Questions ebook cover
PAIRS WELL WITH

550+ FPGA Interview Questions

570 answered questions on FPGA architecture, RTL, timing closure, clocking, memories, AXI and lab debug, with 25 coding exercises. CDC is one of the most common causes of FPGA lab bugs, so the two books work well together.

See the FPGA ebook

550+ CDC Interview Questions

580 questions, 27 chapters, every one answered. Instant PDF download.

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QUESTIONS ABOUT THE BOOK
Does this ebook include answers?

Yes. All 580 questions come with an answer written the way you should say it in an interview, plus a specific interview tip. The 20 coding exercises include complete SystemVerilog solutions.

What format do I get, and how do I receive it?

A 152-page PDF, delivered as an instant download through Topmate right after checkout.

Is a whole book on CDC too narrow?

No. CDC comes up in RTL design, verification, SoC integration, FPGA and STA interviews, and it's where many real silicon bugs come from. The book goes from metastability basics to RDC, constraints, implementation, verification and low-power crossings.

I'm a fresher. Is this too advanced for me?

No. Chapters 1 to 5 build the core: metastability, MTBF, clock relationships, two-flop synchronizers and pulse crossings. 120 questions are marked Beginner, and the rapid-fire round in Chapter 26 is all beginner level.

Does it cover CDC tools and verification?

Yes. Two chapters cover structural CDC analysis, waivers, an annotated CDC tool report, metastability injection, CDC-aware simulation and formal checks, in tool-neutral terms that apply to any commercial CDC flow.

Is there a free preview?

Yes. Twelve real pages are on this page, and the free CDC Interview Questions page has 90+ sample questions, worked answers with code, solved numericals and an MTBF calculator.

What's your refund policy?

Because this is a digital product delivered instantly, sales are generally final. If you hit a technical issue with your download, contact us within 7 days. See our Refund Policy for details.

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