Walk into your next chip design interview actually ready.

Data launched on one edge has to arrive, and be stable for the setup window, before the next edge.

• Tclk ≥ Tclk-q + Tlogic + Tsetup = 0.3 + 3.1 + 0.2 = 3.6 ns, so f_max ≈ 278 MHz.
• Where skew fits in: positive skew at the capture flop relaxes setup; negative skew tightens it.
• Hold is checked separately, and changing the clock frequency does not fix it.

Think about which value of b the second statement reads in each case.

• Blocking: c reads the new b, so both registers load a on the same edge. There's no pipeline stage between them.
• Non-blocking: every right-hand side is sampled before any update, so c gets the old b. That's a two-stage shift register.
• The rule behind it: non-blocking for sequential logic, blocking for combinational logic. This avoids simulation races and simulation/synthesis mismatches.

Compare the width of the pulse with the destination clock period.

• The pulse is 10 ns wide, but the destination samples only every 40 ns, so it can fall between two capture edges. A synchronizer handles metastability. It can't recover an event it never sampled.
• Fix: convert the pulse into a toggle in the source domain, synchronize the level, then edge-detect it in the destination (a pulse synchronizer). Alternatively, use a req/ack handshake.
• Bonus: stretching the pulse works only if you can guarantee a minimum spacing between pulses.

One of them is a uvm_object, and the other is a uvm_component.

• A sequence is a transient uvm_object that generates sequence items, which is the stimulus itself.
• A sequencer is a uvm_component that lives in the testbench hierarchy. It arbitrates between running sequences and hands items to the driver through seq_item_port/seq_item_export.
• Why it matters: keeping them separate lets you swap stimulus without touching the environment.

Look at whether the clock period appears anywhere in the hold equation.

• For same-edge paths, the hold check compares data arrival with the same clock edge, so the period drops out. A slower clock changes nothing.
• Fixes: insert delay cells or buffers on the data path, swap to slower or higher-Vt cells, or rework skew on the offending clock branches.
• Check that every hold fix leaves setup margin, and fix hold at the correct (fast) corner.

Think about what makes a fault model useful for ATPG, even when it isn't physically exact.

• It assumes a single net is permanently tied to logic 0 or logic 1.
• It's simple enough for ATPG to target efficiently and gives a clear coverage metric. Patterns that catch stuck-at faults also catch many real defects.
• Its limits: it misses timing-related defects, which is why transition and path-delay fault models are added on top.

Think about what a flip-flop does when its input changes inside the setup/hold window.

• A flop that samples a changing input can sit at an intermediate level and resolve late, to either 0 or 1.
• A synchronizer gives it extra time (a clock period) to resolve before anyone uses the value. The failure probability falls exponentially with that time, so MTBF rises sharply, but it never becomes zero.
• MTBF depends on resolution time, the flop's time constant and the clock and data rates. More stages or faster flops raise it.

One of them is just storage. The other also coordinates two processes.

• A queue is a data structure: push, pop, index. It does no synchronization, so a reader must check whether it is empty.
• A mailbox is a synchronization class: get() blocks until an item arrives, and a bounded mailbox's put() blocks when it is full.
• Use a mailbox between concurrent threads such as a generator and a driver; use a queue for storage, like a scoreboard's list of expected items.

Which two clock edges does each check compare?

• Setup compares the launch edge with the next capture edge, one period later, so a longer period gives more slack.
• Hold compares launch and capture on the same edge: new data must not arrive before the capture flop's hold window ends. The period never appears in the equation.
• That is why a hold violation can't be fixed by slowing the clock. You add delay on the data path or adjust skew.

Think about the path, the field name, the type, and when each call runs.

• It passes configuration between components through the hierarchy, most often the virtual interface from the top module down to drivers and monitors.
• A get() succeeds only if the type, field name and hierarchical path all match a set(). A typo in the path or a different parameterization silently misses.
• Order matters: the set() must run before the consumer's build phase. Always check the return value and raise a fatal error if it fails.

What goes wrong when standard cells crowd right up against a macro's pins?

• A halo keeps standard cells away from the macro edge so the router can reach the macro pins.
• It reduces congestion at macro edges and corners, where many nets converge.
• It also leaves room for buffers and reduces noise coupling near sensitive macros. Channels between macros must be sized for the routing through them.

What does a global reset cost in routing, and what state does an FPGA start in anyway?

• A reset reaching every register is a huge-fanout net that uses routing resources and can hurt timing.
• FPGA registers start from known values after configuration, so many datapath registers do not need a functional reset.
• Resets can also block efficient mapping, for example into shift-register LUTs or DSP pipeline registers. Reset the control path; leave the datapath free.

You need to remember the previous value of the signal.

• Register the signal: sig_d <= sig; then pulse = sig & ~sig_d;
• If the signal comes from another clock domain, synchronize it first and edge-detect the synchronized version.
• Falling edge is ~sig & sig_d; any edge is sig ^ sig_d.

Which one is allowed to consume simulation time?

• A function runs in zero time: no #, @ or wait. It returns a value and can be used inside expressions.
• A task can contain timing controls and returns results through output arguments rather than a return value.
• Both are synthesizable when they contain no timing controls. Tasks are common in testbenches for driving bus transactions.

One part depends on switching activity, one on short overlaps, and one exists even when nothing switches.

• Dynamic switching power, roughly α·C·V²·f, is usually the largest share in active logic. Reduce it with clock gating, lower voltage (DVFS) and less switching activity.
• Short-circuit power flows briefly while both networks conduct during a transition; sharp input slews keep it small.
• Leakage flows even when idle. Reduce it with high-Vt cells, power gating and body biasing.

Where are the flops physically, compared with the order they were stitched in?

• Initial scan stitching ignores physical location, so consecutive flops can be far apart, creating long wires and congestion.
• After placement, the tool reorders the chain so neighbouring flops connect, cutting wirelength and routing load.
• Constraints still apply: keep clock domains and edges consistent, use lock-up latches where domains meet, and update the scan definition for ATPG.

What keeps the run phase alive?

• No objection was raised, so the run phase ended immediately.
• Raise an objection before starting the sequence and drop it after the sequence (and any drain time) finishes.
• Also check the sequence was started on a real sequencer handle, not a null one.

Start with changes that touch only cells, and end with changes to the design itself.

• First confirm it is a real path, not a missing false-path or multicycle constraint.
• Cell-level fixes: upsize drivers, swap to lower-Vt cells, buffer long wires, reroute on faster layers.
• Bigger changes: restructure or retime logic, use useful skew on the capture clock, and finally add a pipeline stage.

Look for things RTL simulation forgives but hardware does not.

• Missing default branches or full_case/parallel_case pragmas can cause simulation/synthesis mismatches.
• The state register may not be reset, or reset is de-asserted asynchronously without synchronization.
• Synthesis may re-encode the states, for example to one-hot; make sure illegal states recover to a safe state.

What does == return when one operand contains X?

• == returns X if either operand has an X or Z bit; === compares X and Z literally and always returns 0 or 1.
• An if treats X as false, so a check built on == can silently skip a real failure.
• Use ===/!== or $isunknown in testbench checks; keep them out of synthesizable RTL.

When does the parent process continue in each case?

• join waits for every child; join_any continues when the first finishes, leaving the rest running; join_none continues immediately.
• Use disable fork or wait fork to control the leftover threads.
• Classic bug: in a loop with join_none, copy the loop variable into an automatic variable, or every thread sees the final value.

You can weaken the aggressor's effect, strengthen the victim, or separate them.

• Identify the victim nets and their aggressors, and check whether their switching windows overlap.
• Separate them: extra spacing or non-default rules, shielding, or moving the victim to another layer.
• Strengthen the victim: upsize its driver or add buffers to shorten the net and sharpen transitions.

What happens during shift if the two clocks arrive with skew?

• During shift, clock skew between domains can make the next segment capture data too early, a hold violation at the boundary.
• A lock-up latch, transparent on the opposite clock phase, adds half a cycle of delay and removes the race.
• The alternative is to keep separate chains per clock domain.

Count how many states each style gets from n flops.

• Binary: 4 flops, since 2&sup4; = 16 ≥ 10 (with logic to skip six states).
• Johnson: 5 flops, since a Johnson counter has 2n states.
• One-hot: 10 flops. More flops, but simpler, glitch-free decoding and fast next-state logic.

One is a difference in space, the other a variation in time.

• Skew is the difference in clock arrival between two flops; jitter is the edge-to-edge variation of one clock over time.
• Setup: jitter shrinks the usable period; positive skew at the capture flop helps setup, negative skew hurts it.
• Hold: launch and capture use the same edge, so cycle-to-cycle jitter largely cancels, while positive skew hurts hold. Tools still apply a hold uncertainty as margin.

What happens if the enable changes while the clock is high?

• Clock gating stops the clock to idle registers, saving dynamic power.
• With a plain AND gate, an enable that changes while the clock is high creates glitches, and so extra clock edges.
• An integrated clock-gating cell latches the enable during the low phase, so the gated clock stays clean. Synthesis inserts these cells from enable-style RTL.

Which components does each create?

• An active agent has a sequencer, a driver and a monitor, and drives stimulus into the DUT.
• A passive agent has only a monitor (and often coverage). It observes interfaces the testbench does not drive.
• The is_active setting decides what the build phase creates, so the same agent can be reused at block and system level.

Coverpoints capture single conditions; a cross captures combinations.

• Coverpoints on the full and empty flags, each with bins for 0 and 1.
• A cross of write-enable with full to catch the write-while-full case.
• Sample on the clock. Coverage shows what was exercised, not whether it behaved correctly; pair it with assertions.

It happens during manufacturing, before the chip is complete.

• During plasma etching, a long metal wire connected only to a transistor gate collects charge that can damage the thin gate oxide.
• The risk is measured as the ratio of metal area to gate area, checked against foundry rules.
• Fixes: jump to a higher metal layer to break the long wire, add an antenna diode near the gate, or insert a buffer.

Think about size, read latency and what else those LUTs could be doing.

• Block RAM is dedicated memory with synchronous reads, best for larger buffers.
• Distributed RAM is built from LUTs: small, can read asynchronously, but consumes logic resources.
• Your coding style decides what synthesis infers, for example a registered read address or output maps to block RAM.

Start from the fault classes ATPG reports, not from the logic.

• Check the untestable and not-detected fault classes; some faults are genuinely redundant.
• Common causes: clocks or resets not controllable in test mode, non-scan flops, black-boxed memories, and X sources.
• Fixes: make clocks and resets controllable, scan the remaining flops, bypass or model the memories, and add control and observe test points.

Look at which transistors end up in series in each gate.

• A NOR gate stacks PMOS transistors in series in the pull-up; a NAND gate stacks NMOS instead.
• PMOS has lower carrier mobility, so series PMOS must be made much wider to match drive strength.
• That makes NOR gates larger, slower and heavier loads on their inputs, so NAND-based logic is preferred.

Where does the write side's copy of the read pointer come from?

• No. The read pointer reaches the write domain through a synchronizer, so the write side sees an older value.
• A stale read pointer makes the FIFO look fuller than it is: full releases late. That is safe; it never overflows, it only costs a little throughput.
• The unsafe case would be full releasing early. Gray-coded pointers make sure only one bit changes as they cross domains.

Removing a timing check doesn't make the path safe; it only stops the tool from checking it.

• It removes timing analysis on the specified paths.
• It is appropriate for paths that are genuinely not timed: static configuration signals or crossings protected by proper synchronizers.
• It is dangerous when it hides a real functional path, or when a broad clock-to-clock false path hides bus skew. For CDC buses, bound the delay instead with set_max_delay.

Some differences come from how RTL was written, others from timing.

• Simulation/synthesis mismatch: incomplete sensitivity lists, blocking assignments in sequential logic, or case pragmas.
• Registers without reset that RTL happened to tolerate, or X-optimism in RTL if/case hiding unknowns.
• Timing violations in SDF-annotated simulation, which drive flops to X.

How many components might want the same transaction?

• The monitor calls write() on an analysis port, which broadcasts to every connected subscriber: scoreboard, coverage and others.
• The monitor stays unaware of who is listening, so it can be reused anywhere, with zero or many listeners.
• Send a copy of each transaction, so a later change in the monitor doesn't alter what the scoreboard already received.

Both are inserted before placement, and neither implements logic.

• Well-tap cells tie the n-well to VDD and the substrate to VSS at regular intervals, preventing latch-up.
• End-cap cells sit at the ends of each row to terminate the wells correctly and satisfy boundary design rules.
• Both are placed right after floorplanning, at spacings defined by the foundry rules.

Start from Y = S′A + SB.

• Four NAND gates: one to invert S, one for NAND(A, S′), one for NAND(B, S), and one to combine the two.
• This works because NAND is a universal gate.
• Follow-up worth knowing: the mux has a static hazard when S changes with A = B = 1; the consensus term A·B removes it.

Setup and hold are each worst at a different corner.

• Typical is not a sign-off corner. Setup is usually worst at the slow corner (slow process, low voltage); hold at the fast corner (fast process, high voltage).
• Temperature matters too; at advanced nodes, slow can occur at low temperature (temperature inversion).
• Combine process and voltage corners with RC extraction corners and on-chip variation derates, analysed together in multi-corner multi-mode STA.

What happens to an X when it is assigned to a bit?

• logic holds 0, 1, X and Z; bit holds only 0 and 1, and X or Z becomes 0.
• Sample a DUT output into a bit and an uninitialized or multiply-driven value silently turns into 0, so checks can pass.
• Use 4-state types for DUT connections and checks; 2-state types are fine for testbench counters and data for speed.

Rule out constraint problems first.

• Check the constraints: clock definitions, I/O delays, and whether any false-path or multicycle constraint is missing or wrong.
• Let the tools help: enable retiming, duplicate high-fanout registers, and use dedicated carry chains and DSP blocks.
• Then floorplan critical logic closer together, and only then add pipeline stages.

What does a powered-down block's output look like to a block that is still on?

• Isolation cells clamp the outputs of a powered-down domain to a known value, so floating signals don't cause X propagation or crowbar current in the domain that stays on.
• Level shifters translate signals between domains running at different voltages.
• Both are specified in the power intent (UPF), along with retention registers that keep state through power-down.