The silicon die
The chip that matters: transistors and a stack of metal wiring on a thin slab of silicon. A die might be anywhere from a few square millimetres to more than 800 mm². The rest of the package exists to serve it.
Open any packaged chip and you'll find a silicon die, the connections that carry its signals out, a package, and the pins or balls that meet the board. Zoom further and you reach functional blocks, standard cells, transistors and, eventually, atoms. This guide walks through every level with diagrams, real numbers, a yield calculator and a self-check quiz. Along the way, it shows which VLSI job works on each level.
Seals and protects everything inside. It's the part shown lifting open.
Carry every signal and all the power off the die.
The actual chip: up to billions of transistors on a slab of silicon.
Where the package meets the circuit board.
From a whole board down to a single atom is roughly a factor of a billion. Step through each level: what you'd see, how big it is, and who designs it.
Your chip is one of dozens of parts on a printed circuit board: voltage regulators, memory, crystals and connectors. Copper traces inside the board's layers carry power and signals between them. At this level, the chip is just one rectangle on the board's layout.
What most people call “the chip” is really the package. It protects the die and translates pitch: pads on the die sit tens of micrometres apart, while solder balls on the board sit around a millimetre apart. The substrate inside fans every connection out from one scale to the other.
Under the lid is a slab of crystalline silicon: the die. Everything that computes lives in a layer only a few micrometres thick on its top surface. The rest is mechanical support. A single lithography exposure can only pattern about 26 × 33 mm, so no normal die can be larger than roughly 850 mm².
Zoom into the die and it resolves into blocks, like districts in a city: CPU cores, a GPU, an AI accelerator, big SRAM caches, memory controllers, and analog PHYs that talk to the outside world. On many chips, SRAM takes up a large share of the area.
Each digital block is built from standard cells: pre-designed gates such as NAND, NOR, flip-flops and buffers. They're all the same height, so they snap into rows. The rows share power rails, and alternate rows are flipped so neighbouring rows can share a VDD or VSS rail.
Each gate is a handful of transistors: an inverter is 2, a NAND2 is 4, and a typical flip-flop is roughly 20 or more. A modern transistor is a FinFET or a gate-all-around (GAA) nanosheet. The gate wraps the channel on three or four sides, so it can switch current off sharply and leak less.
At the bottom is the silicon crystal. Its repeating unit, the lattice constant, is 0.543 nm. A fin or nanosheet a few nanometres thick is only a few tens of atoms across. At that size, a few misplaced atoms measurably change a transistor. That's why process variation and on-chip-variation margins exist.
Cut any package open and you'll find these four layers, whether it's a laptop processor or a sensor in a smartwatch. What changes from chip to chip is how each layer is built.
The chip that matters: transistors and a stack of metal wiring on a thin slab of silicon. A die might be anywhere from a few square millimetres to more than 800 mm². The rest of the package exists to serve it.
Signals leave the die through thin gold, copper or aluminium bond wires, welded one at a time by ultrasonic bonders. High-performance chips are instead flipped face-down onto thousands of solder or copper bumps: shorter paths, more connections, and better power delivery.
A small multi-layer circuit board, the substrate, routes every die connection outward. Mould compound or a metal lid seals the die from moisture and knocks, and a heat spreader carries heat away.
The only part you ever touch. It might be legs on a DIP, flat pads on a QFN, or hundreds to thousands of solder balls on a BGA. On high-power chips, a large share of them carry nothing but power and ground.
ILLUSTRATIVE CROSS-SECTIONS. NOT TO SCALE.
Wire bonding places the die face-up and connects only its edge pads. The number of connections grows with the die's perimeter, and each wire adds a few nanohenries of inductance. That's fine for a microcontroller.
Flip-chip places the die face-down on an array of bumps covering its whole area. The number of connections grows with area instead, so a large processor can dedicate thousands of bumps just to power and ground. Heat also escapes through the exposed back of the die.
A system-on-chip (SoC) is organised like a city: compute districts, memory warehouses, and a ring of ports around the edge. The layout below is a typical arrangement, not any specific product.
ILLUSTRATIVE FLOORPLAN. REAL DIES DIFFER.
| BLOCK | WHAT IT DOES | HOW IT'S BUILT | STUDY |
|---|---|---|---|
| CPU cores + L1/L2 | Run the operating system and general code. Each core has private L1/L2 caches. | Digital, largely synthesised. Critical paths are often hand-tuned. | RTL, STA, PD |
| GPU / NPU | Massively parallel maths for graphics and AI. Many identical compute units are replicated across the block. | Digital. Built as a hierarchical design with replicated partitions. | Verification, PD |
| Shared cache (SRAM) | Keeps hot data on-chip, because going to DRAM costs far more time and energy. | Memory compiler macros with redundancy repair. | DFT (MBIST) |
| Interconnect / NoC | Moves data between all the blocks: the chip's road network. | Digital, with a lot of timing and CDC work. | CDC, STA |
| DDR / SerDes PHYs | Send and receive multi-gigabit signals to DRAM, PCIe, USB and Ethernet. | Mixed-signal. Usually licensed IP, and they sit on the die edge. | Analog, IP |
| PLLs & clocking | Create the fast clocks every flip-flop runs on, from a slow crystal reference. | Analog / custom. | PLL, jitter |
| PMU, sensors, security | Voltage and frequency control, temperature sensors, fuses and the boot ROM. | Mixed. | DVFS, low power |
| I/O pad ring | ESD protection, level shifting and drivers for every signal that leaves the die. | Custom I/O library cells. | Level shifter, latch-up |
Synthesis turns RTL into a netlist of cells from a library. Placement then lines those cells up in rows, like books on shelves. Every cell has the same height, and the width depends on what the cell does and how strong it is.
Cell height is given as a number of metal-routing tracks, for example a 6- or 7.5-track library. Shorter cells are denser. Taller cells have room for stronger transistors and are easier to route.
A library can contain thousands of cells: the same NAND2 in X1, X2 and X4 drive strengths, and in low, standard and high threshold-voltage flavours. That lets tools trade speed against leakage, one cell at a time.
Filler cells keep the rows continuous. Tap cells tie the wells to prevent latch-up. Decap cells store charge to steady the local supply.
A MOSFET is a switch: voltage on the gate opens or closes a channel between source and drain. As transistors shrank, a gate on just one side of the channel could no longer switch it off cleanly, and leakage soared. The fix was to wrap the gate around more of the channel.
The gate sits on top of a flat channel and controls it from one side. As channels shortened, leakage rose and control weakened.
The channel stands up as a thin fin, and the gate wraps three sides. It entered high-volume production with Intel's 22 nm process in 2011–12, and the rest of the industry followed.
Stacked horizontal nanosheets, each fully surrounded by the gate. Samsung's 3 nm (2022) came first, followed by TSMC's N2 and Intel's 18A (RibbonFET) generations.
Complementary MOS pairs an nMOS network, which pulls the output down to VSS, with a pMOS network, which pulls it up to VDD. In steady state one network is off, so ideally no current flows. Power is mostly spent when the output switches (dynamic power, roughly α·C·V²·f), plus leakage.
That's why the biggest power savings come from lowering voltage, and from not switching at all: clock gating and power gating.
The transistors sit in a single layer at the bottom. Above them, a dozen or more layers of copper wires, joined by vertical vias, connect billions of cells. This is the back end of line (BEOL), and on modern chips the wires, not the transistors, often decide speed and power.
SCHEMATIC CROSS-SECTION. WIRES RUN INTO THE PAGE, AND ALTERNATE LAYERS RUN AT RIGHT ANGLES. NOT TO SCALE.
Chip features sit between biology and chemistry: far smaller than a cell, still larger than an atom. These figures are approximate and vary by process and source. They're here to build intuition, not for a spec sheet.
| THING | APPROX. SIZE | WHY IT MATTERS |
|---|---|---|
| Human hair (width) | ~50–100 µm | About 1,500 leading-edge gate pitches fit across one hair. |
| Red blood cell | ~7–8 µm | Roughly the thickness of an entire die's metal stack. |
| Typical bacterium | ~1–2 µm | A few standard-cell rows tall. |
| DUV lithography light (ArF) | 193 nm | Used for most layers. Tight layers need multiple exposures. |
| Contacted gate pitch, leading edge | ~45–50 nm | The centre-to-centre spacing of transistor gates. Far larger than “3 nm”. |
| Tightest metal pitch, leading edge | ~20–30 nm | The densest wires on the chip, in the M0–M2 layers. |
| EUV lithography light | 13.5 nm | The shorter wavelength prints the finest layers in one exposure. |
| Fin or nanosheet thickness | ~5–7 nm | Only a few tens of atoms thick. |
| Silicon lattice constant | 0.543 nm | The crystal's repeating unit. It's the hard floor on how small things can go. |
A leading-edge wafer goes through hundreds to more than a thousand process steps, and spends a few months in the fab. Most steps repeat the same loop: pattern, etch or deposit, clean, measure.
Silicon is refined to extreme purity, better than 99.9999999% for electronics. It's then grown into a single-crystal ingot by slowly pulling a seed from molten silicon (the Czochralski process).
The ingot is sliced into wafers, now mostly 300 mm across and under 1 mm thick, and polished flatter than almost any other surface humans make.
A light-sensitive resist is exposed through a mask (reticle) to print one layer's pattern. Critical layers at leading nodes use 13.5 nm EUV light. Most others use 193 nm DUV immersion.
Material is removed where the pattern says, and new films are added. Atomic-layer deposition can grow films one atomic layer at a time.
Ion implantation fires dopant atoms into the silicon, and an anneal activates them. This sets where the n-type and p-type regions are.
Repeating steps 3–5 many times builds the transistors: fins or nanosheets, gate stacks, sources and drains.
Layer after layer of copper wiring and vias is built with the damascene process, and each layer is polished flat (CMP) before the next one.
Every die is probed on the wafer. Failing dies are recorded on a wafer map so they're never packaged. Test structures in the scribe lines are measured too.
The wafer is thinned, then sawn or laser-cut along the scribe lines. Good dies are attached to a package and connected by wire bond or flip-chip, then sealed.
Packaged parts are tested again, sometimes stressed at high temperature and voltage, and sorted (binned) by speed and power into different products.
Choose a die size and a defect density. The wafer map shows how many whole dies fit on the wafer. Random defects then land on it: any die that catches one fails. That's why large dies cost disproportionately more, and why the industry moved to chiplets.
Assumes a 3 mm edge exclusion and 0.1 mm scribe lines. Yield = e−A·D₀, the simplest textbook model. Real fabs use more detailed models, and account for systematic defects and on-chip repair.
A single exposure field caps a die at roughly 26 × 33 mm, and large dies yield poorly. So the biggest processors combine several dies in one package, linked far more densely than a circuit board could manage. This is how most AI accelerators are built today.
SCHEMATIC 2.5D PACKAGE: A LOGIC DIE AND HBM ON A SILICON INTERPOSER. NOT TO SCALE.
| APPROACH | INTERCONNECT (TYPICAL) | WHERE YOU SEE IT | TRADE-OFF |
|---|---|---|---|
| Wire bond (QFN, QFP, BGA) | Edge pads, ~40–100 µm pitch | Microcontrollers, analog, power, sensors | Cheapest and most mature. Few I/Os, and wires add inductance. |
| Flip-chip BGA | Area array bumps, ~100–200 µm | CPUs, GPUs, networking | Thousands of connections and good power delivery. Costs more. |
| Fan-out wafer-level | Redistribution layers, no substrate | Phone application processors, RF | Thin and cheap per I/O. Used by many phone SoCs. |
| 2.5D interposer | Micro-bumps, ~40–55 µm | AI accelerators with HBM | Huge bandwidth between dies. The interposer is expensive and capacity-limited. |
| 3D stacking / hybrid bonding | Direct Cu–Cu, <10 µm | Stacked cache, image sensors, HBM | Densest links. Harder thermal problems and test challenges. |
Pitches are rough, order-of-magnitude figures. They vary by vendor and generation.
Split a design into smaller dies. Compute can use the newest node while I/O stays on a cheaper one. Standards such as UCIe define die-to-die links. See chiplet.
Through-silicon vias are vertical copper plugs that pass right through a thinned die. They make HBM stacks and 3D integration possible.
Dies are bonded face-to-face with direct copper pads at a pitch of micrometres. It's used for stacked caches on processors and in image sensors.
A high-end processor draws hundreds of amperes at under a volt. Delivering that current without the voltage sagging, and then removing the heat, shapes the whole chip from package to metal stack.
What PD engineers check: IR drop, electromigration, decap placement and supply noise.
Data-centre GPUs are now rated at around 700 W or more per package, which is why liquid cooling is spreading. On-die sensors drive DVFS and throttling.
Every VLSI role owns one or more of the zoom levels above. Once you know which level an interview question is about, it gets much less abstract.
| ROLE | LEVEL | WHAT THEY DECIDE | PREPARE WITH |
|---|---|---|---|
| Architecture & SoC | Blocks | What blocks exist, how big the caches are, and the performance and power targets. | VLSI · ASIC |
| RTL design | Blocks → cells | The logic itself, written in Verilog/SystemVerilog. | RTL · Verilog |
| Design verification | Blocks | Proving the RTL does what the spec says, before silicon. | SV · UVM |
| Synthesis & STA | Cells | Turning RTL into cells, and proving every path meets timing across corners. | STA |
| Physical design | Cells → metal | Floorplan, placement, clock tree, routing, IR drop and sign-off. | PD |
| DFT | Every level | Scan, ATPG, MBIST and boundary scan, so every die and package can be tested. | DFT |
| Analog / mixed-signal | Blocks → transistor | PLLs, PHYs, ADCs and regulators, hand-designed at the transistor level. | Analog |
| Device & process | Transistor → atoms | Building transistors that switch fast, leak little and yield well. | CMOS · Semiconductor |
| Packaging, SI/PI, test | Package → board | Substrates, bumps, power delivery, signal integrity and production test. | Semiconductor · DFT |
| FPGA / prototyping | Blocks | Running the RTL on FPGAs before silicon exists. | FPGA |
That's the package. The chip, the die, is usually a much smaller piece of silicon hidden inside it.
Node names are generation labels. The gate pitch at a “3 nm” node is around 45–50 nm, and the tightest metal pitch is roughly 20–30 nm.
The transistors form one layer, but above them sit a dozen or more metal layers, and advanced packages stack whole dies on top of each other.
Defects are statistical. Yield, wafer sort and binning exist because some dies fail, and some work but only at a lower speed.
Performance also depends on architecture, memory bandwidth, clock speed and power limits. Many transistors go into caches and I/O, not compute.
Each wafer carries dozens to thousands of dies, and wafers move through the fab in batches. What costs time is the hundreds of process steps.
Click an answer to see whether it's right, and why. Nothing is stored or sent anywhere. For a longer, timed test, try the VLSI quiz.
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The substrate fans every connection out from the die's fine pitch to a pitch a PCB can be soldered to. That's why substrates have many routing layers.
A fixed height (measured in metal tracks) lets placement tools line cells up in rows, where they share power rails. Width varies with the function and drive strength.
Planar gates control the channel from one side, and FinFET gates from three. GAA nanosheets are fully surrounded, which gives the best electrostatic control.
Resistance drops as a wire gets wider and thicker. Long routes, clocks and the power grid use the upper layers. The tight lower layers handle short local connections.
With a Poisson model, yield is e^(−A·D₀). A bigger area means a higher chance of catching a killer defect, which is one reason chiplets exist.
High Bandwidth Memory stacks DRAM dies and connects them with TSVs, then sits next to the processor on an interposer. That gives very wide, short links.
Node names don't describe any single physical dimension any more. The gate pitch at leading nodes is in the mid-40s to around 50 nm.
Probe cards contact each die on the wafer. Failing dies are recorded on a wafer map, so money isn't spent packaging them.
It ranges hugely. Intel's 4004 (1971) had about 2,300. A small microcontroller today has millions. Apple's M3 Ultra has about 184 billion across two joined dies. NVIDIA's Blackwell B200 GPU has about 208 billion across two dies in one package. Cerebras' wafer-scale WSE-3, a single processor the size of a whole wafer, has about 4 trillion.
A wafer is the round silicon disc, now usually 300 mm across, that the fab processes. It holds many identical dies, which are cut apart after testing. A chip, in everyday use, is a packaged die, or sometimes several dies in one package.
The die is crystalline silicon with doped regions, very thin insulating films and metal gates, wired together by copper interconnect in a low-k dielectric. The top pads are often aluminium. The package adds an organic or ceramic substrate, mould compound or a metal lid, solder (tin-based alloys) and sometimes gold or copper bond wires.
It's a generation name, not a measurement. Around the 28–22 nm era, node names stopped matching any single feature size. Better figures are the contacted gate pitch (around 45–50 nm at leading nodes), the minimum metal pitch (around 20–30 nm) and transistor density. See process node.
Simple, older-node chips may have 4–6. Leading-edge logic commonly has a dozen or more, often around 15 or more, from ultra-fine local layers at the bottom to thick power and global-routing layers at the top.
A bare die is fragile and sensitive to moisture and static, and its pads are far too fine to solder onto a normal board. The package protects it, spreads its heat, and fans its connections out to board scale.
Wire bonding connects pads around the die's edge with thin wires, with the die face-up. It's cheap and mature. Flip-chip turns the die face-down onto bumps spread across its whole area. That gives far more connections, shorter paths and better power delivery, so almost all high-performance processors use it.
A chiplet is a smaller die designed to be combined with others in one package, instead of building one giant die. Smaller dies yield better, and each chiplet can use the process node that suits it best. Standards like UCIe aim to let chiplets from different vendors talk to each other. See chiplet.
Two reasons. Fewer big dies fit on a wafer, especially near the round edge. And each die has a higher chance of catching a killer defect. Try the yield calculator above: doubling die area can cut the number of good dies per wafer by more than half.
Power flows from the board's regulators through many power and ground balls, through planes in the substrate, into bumps, down through the thick top metal layers, into a fine power grid, and finally into the rails of every standard-cell row. Designers must keep IR drop and electromigration within limits. Newer processes are moving power delivery to the back of the wafer.
Designing a large chip typically takes one to three years. Manufacturing a leading-edge wafer takes a few months: hundreds to more than a thousand process steps in the fab, followed by assembly and test.
Dies that fail wafer sort are never packaged. Many chips build in repair: spare SRAM rows and columns are swapped in using fuses after memory self-test. Some dies with a faulty core or lower top speed are sold as lower-tier products (binning or harvesting).
Engineers “decap” packages with acids or lasers in failure-analysis labs. That's hazardous, so don't try it at home. Published die photos and teardown analyses are a safe way to see real floorplans.
Start with digital logic and Verilog, then pick a direction: RTL design, verification, physical design, DFT or analog. The career roadmaps and tutorials lay out the steps, and the question banks show what interviews expect.
Figures are approximate and drawn from public manufacturer announcements and widely published industry data. Process details vary by foundry and generation.
Each zoom level maps to a question bank, with worked answers on the core topics.