| SystemVerilog | 1,527 | Questions only | Verification roles, OOP and constrained-random rounds | On Topmate | PreviewGet the ebook now: SystemVerilog (opens in a new tab) → |
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| General VLSI | 1,455 | Questions only | Freshers, plus company-specific question sets | On Topmate | PreviewGet the ebook now: General VLSI (opens in a new tab) → |
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| UVM | 616 | Questions only | DV engineers who already know some SystemVerilog | On Topmate | PreviewGet the ebook now: UVM (opens in a new tab) → |
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| Physical Design | 616 | Yes, full answers | PD and STA roles; self-study without a mentor | On Topmate | PreviewGet the ebook now: Physical Design (opens in a new tab) → |
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| STA | 621 | Yes, full answers | STA, PD and signoff roles: numericals, SDC, reports | On Topmate | PreviewGet the ebook now: STA (opens in a new tab) → |
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| FPGA | 570 | Yes, full answers | FPGA roles: RTL, timing, CDC, memories, AXI, debug | On Topmate | PreviewGet the ebook now: FPGA (opens in a new tab) → |
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| CDC | 580 | Yes, full answers | RTL, DV, SoC and FPGA roles: synchronizers, FIFOs, RDC | On Topmate | PreviewGet the ebook now: CDC (opens in a new tab) → |
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| Digital Electronics | 581 | Yes, full answers | First technical round: logic, flip-flops, timing, FSMs | On Topmate | PreviewGet the ebook now: Digital Electronics (opens in a new tab) → |
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| CMOS | 580 | Yes, full answers | Circuit, memory, PD and STA roles: devices, sizing, power | On Topmate | PreviewGet the ebook now: CMOS (opens in a new tab) → |
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| Semiconductor Devices | 580 | Yes, full answers | Device, process, TCAD and reliability roles: device physics | On Topmate | PreviewGet the ebook now: Semiconductor Devices (opens in a new tab) → |
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| Verilog | 580 | Yes, full answers | RTL, DV and FPGA roles: language rules, coding and debug | On Topmate | PreviewGet the ebook now: Verilog (opens in a new tab) → |
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| Analog VLSI | 580 | Yes, full answers | Analog, mixed-signal and analog layout roles: circuits, stability and noise | On Topmate | PreviewGet the ebook now: Analog VLSI (opens in a new tab) → |
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| ASIC Design | 580 | Yes, full answers | RTL, DV, PD, STA and DFT roles: the full flow from spec to silicon | On Topmate | PreviewGet the ebook now: ASIC Design (opens in a new tab) → |
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| DFT | 575 | Yes, full answers | DFT roles: scan, ATPG, compression, BIST, JTAG | On Topmate | PreviewGet the ebook now: DFT (opens in a new tab) → |
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| RTL Design | 550 | Questions only | RTL and design roles: coding, FSMs, CDC, synthesis | On Topmate | PreviewGet the ebook now: RTL Design (opens in a new tab) → |