Fifteen ebooks, one per major VLSI track
Every cover is a real preview — click to zoom in and read it before you decide. Each ebook page also has free sample pages from inside the book.
Answered, for self-study without a mentor
Every question has an interview-ready answer and an interview tip. STA, DFT, FPGA, CDC, Digital Electronics, CMOS and Semiconductor Devices also include solved numericals; FPGA, CDC and Digital Electronics add coding exercises, CMOS adds SPICE circuit exercises, Semiconductor Devices adds Python and SPICE device labs, Verilog adds 20 coding exercises and 25 predict-the-output puzzles, Analog VLSI adds 20 SPICE exercises and 25 solved numericals, and ASIC Design adds 20 open-source flow exercises and 25 numericals.
550+ Physical Design Interview Questions
Floorplanning through tapeout sign-off — every question includes a full answer, explanation, and interview tip
550+ STA Interview Questions
Setup/hold, 25 solved numericals, SDC, OCV/CPPR, MCMM, crosstalk, timing reports — every question answered with an interview tip
550+ DFT Interview Questions
Fault models, scan, ATPG, at-speed, compression, LBIST, MBIST, JTAG/IJTAG, diagnosis — every question answered with an interview tip
550+ FPGA Interview Questions
Architecture, RTL, 25 coding exercises, timing closure, CDC, BRAM/FIFOs, DSP, transceivers, AXI, debug — every question answered
550+ CDC Interview Questions
Metastability, synchronizers, handshakes, Gray code, async FIFOs, reconvergence, RDC, constraints — every question answered
550+ Digital Electronics Interview Questions
Number systems, Boolean algebra, K-maps, adders, flip-flops, setup and hold, counters, FSMs, CMOS, memories, Verilog — every question answered
550+ CMOS VLSI Design Interview Questions
MOSFETs, FinFET, inverter, static and dynamic logic, logical effort, SRAM, interconnect, power, latch-up, ESD, variation — every question answered
550+ Semiconductor Devices Interview Questions
Energy bands, doping, PN and Schottky junctions, BJTs, MOS capacitor, MOSFET, FinFET and GAA, power devices, reliability, process, TCAD — every question answered
550+ Verilog Interview Questions
Data types, widths and signedness, blocking vs non-blocking, event queue, FSMs, FIFOs, CDC, synthesis, testbenches, GLS, lint — every question answered
550+ Analog VLSI Interview Questions
gm/ID, amplifiers, mirrors, differential pairs, op-amps, compensation, noise, bandgaps, LDOs, ADCs, PLLs, layout — every question answered
550+ ASIC Interview Questions
Flow, libraries, RTL, verification, synthesis, SDC, LEC, DFT, UPF, floorplan, CTS, routing, STA, sign-off, yield — every question answered
Questions only, for building recall
Big question banks with no answers printed, so you practise producing the answer yourself, the way an interview works.
1527+ SystemVerilog Interview Questions
OOP · constrained-random · interfaces · coverage · assertions · UVM fundamentals
1500+ General VLSI Interview Questions
Fundamentals · project-based · 10 company-specific sets (Intel, AMD, NVIDIA & more) · mock interviews
550+ RTL Design Interview Questions
Verilog coding · FSM design · timing · CDC · synthesis · real debugging scenarios
550+ UVM Interview Questions
Testbench architecture · Factory · Config DB · sequences · drivers · scoreboards · RAL
Every ebook includes a free preview before you buy. Prefer to sample the format first? Check our free downloads page.