What do general VLSI interviews focus on?

Fundamentals across domains (digital logic, CMOS and power, timing, the design flow, a little fabrication and test), then your project in depth, then questions about the role and company. Domain-specific rounds usually come later.

Which domain should a fresher choose?

The one you can show real interest in. Verification usually has the most openings, RTL and PD reward strong fundamentals, DFT and STA are smaller but in demand. A project in that domain matters more than the choice itself.

How important is the project round?

Very. For freshers it's often the deciding round, because it's the only evidence of what you can actually do. Prepare a two-minute version and answers to ten follow-ups.

Do I need to know Verilog for every role?

For almost every digital role, yes, at least the basics: modules, always blocks, blocking vs non-blocking, a counter and an FSM. Analog roles are the main exception.

How long should I prepare?

With good basics, four to six weeks of steady practice covers fundamentals, your project and one domain. Starting from scratch, plan for two to three months.

Are aptitude and HR rounds part of it?

Often, especially in campus drives. See our VLSI HR interview questions for the behavioural round.

VLSI Interview Questions for Freshers: 90+ Answers

A general VLSI interview, the kind freshers and people changing roles face first, is wide rather than deep. In an hour you can be asked about a flip-flop, a CMOS inverter, the ASIC flow, setup time, how a chip is tested, and then spend twenty minutes on your own project. The interviewer is looking for strong basics, clear thinking and a sense of where you'd fit.

Start with the formula sheet and the roles table, skim the 50 questions by topic, then work through the worked answers and numericals. Spend real time on the project makeover: for most freshers, the project round decides the result.

HOW IT'S ASKED

Three parts of a general VLSI interview

PART 1

Fundamentals across domains

Digital logic, CMOS, power, setup and hold, the design flow, a little fabrication. Each question is easy alone; the challenge is having all of them ready at once.

PART 2

Your project, in depth

What you built, what you did yourself, how you verified it, what went wrong and what you'd change. Follow-ups test whether you really did the work.

PART 3

Role and company fit

Which domain you want and why, what the company builds, and a few questions from that domain to check your interest is real.

HOW TO ANSWER

Six habits of strong VLSI answers

Define, then go one step further

"Setup time is…" is the start. Add why it matters or what breaks without it, and you've answered the follow-up before it's asked.

Draw it

An inverter, a flop with its timing, the design flow as boxes. A sketch shows understanding faster than words.

Connect the domains

Clock gating saves power, adds CTS work and needs DFT handling. Linking topics shows you see the whole chip.

Use numbers

"The slack was −80 ps at 500 MHz" beats "there was a timing problem". Interviewers trust specifics.

Say "I" for your work

In the project round, separate what the team did from what you did. Vague "we" answers invite harder follow-ups.

Think aloud when stuck

"I haven't used that, but I'd expect…" and a reasoned guess beats silence or bluffing every time.

FORMULA SHEET

The numbers every VLSI candidate should be able to work out

Each of these turns up as a quick numerical in written tests or the first technical round.

DYNAMIC POWERP_dyn = α·C·V²·f · voltage matters most because it's squared

STATIC POWERP_leak = V · I_leak · rises steeply with temperature and lower V_t

SETUPT ≥ t_cq + t_logic,max + t_su + uncertainty − skew · f_max = 1 / T_min

HOLDt_cq + t_logic,min ≥ t_h + skew · independent of the clock period

IR DROPΔV = I · R · I ≈ P / V_DD · budgets are often a few percent of V_DD

DIES PER WAFERπ(d/2)² / A − π·d / √(2A)d = wafer diameter, A = die area. The second term removes partial dies at the edge.

YIELDY ≈ e^−D₀·A (Poisson) · bigger dies lose yield exponentially

MOORE'S LAWtransistor count × 2 roughly every two years · N years → 2^N/2

COUNTERS & FSMsmod-N counter: ⌈log₂N⌉ flops · S states: ⌈log₂S⌉ (binary) or S (one-hot)

SCAN TEST TIMEcycles ≈ patterns × (chain length + 1) · time = cycles / f_shift

BAUD DIVISORdivisor = f_clk / (oversampling × baud) · round, then check the error stays under ~2%

TRY IT

Die cost & yield calculator

How many dies fit on a wafer, how many work, and what each good die costs. A favourite fresher numerical.

WAFER DIAMETER (mm)

DIE AREA (mm²)

DEFECT DENSITY (/cm²)

WAFER COST ($)

GROSS DIES–

YIELD–

GOOD DIES–

COST PER GOOD DIE–

VLSI ROLES

What each VLSI role does, and what its first round tests

"Which domain do you want, and why?" comes up in almost every fresher interview. Know the roles well enough to answer it.

ROLE	WHAT YOU DO	FIRST-ROUND FOCUS	PREPARE WITH
RTL design	Write the hardware in Verilog or SystemVerilog from a specification	Coding, FSMs, latches, resets, CDC, synthesis	RTL questions
Design verification	Prove the RTL works: testbenches, stimulus, checkers, coverage	SystemVerilog OOP, constraints, coverage, UVM	SV, UVM
Physical design	Turn the netlist into a manufacturable layout that meets timing	Floorplan, placement, CTS, routing, closure	PD questions
STA / signoff	Write constraints and sign off timing across modes and corners	Setup, hold, SDC, OCV, timing reports	STA questions
DFT	Make the chip testable after manufacturing	Scan, ATPG, fault models, BIST, JTAG	DFT questions
FPGA design	Build and close designs on FPGAs, often for prototyping or products	RTL, timing, resources, CDC, debug on hardware	FPGA questions
Analog / circuit	Design at transistor level: amplifiers, data converters, PLLs, I/O	CMOS devices, op-amps, biasing, noise	Analog questions

BROWSE BY TOPIC

50 general VLSI interview questions across 10 topics

A sample of what general and fresher rounds ask most. The ebook has 1,455 questions, including project, company and mock-interview sets.

VLSI & the Industry

The opening questions.

What does VLSI mean, and what changed when chips reached millions of transistors?
What's the difference between a fabless company, a foundry and an EDA company?
What does a "technology node" number actually describe today?
Why did voltage stop scaling with each new node?
What is an SoC, and what blocks does a typical one contain?

Digital Logic

The first technical round.

Why are NAND and NOR called universal gates?
What's the difference between a latch and a flip-flop, and why do designs prefer flops?
How do Moore and Mealy machines differ?
What is a race condition in a circuit?
How do you simplify a function with a K-map, and what are don't-cares for?

CMOS & Power

Transistors and where the power goes.

How does a CMOS inverter work, and why does it draw little static current?
Why is the PMOS usually wider than the NMOS?
What are the three components of power in CMOS?
How do clock gating and power gating differ?
What is latch-up, and how is it prevented?

Design Flow

From idea to silicon.

Walk me through the ASIC design flow.
What goes into synthesis, and what comes out?
What's the difference between front-end and back-end design?
What is tape-out?
When would you choose an FPGA over an ASIC?

Timing

The concept every domain shares.

What are setup and hold time, and what happens if they're violated?
What is clock skew, and is it always bad?
What is metastability, and how does a synchroniser help?
What's the difference between static and dynamic timing analysis?
What are PVT corners?

Verification

How bugs are found before silicon.

Why does verification take more effort than design on most chips?
What's the difference between directed and constrained-random testing?
What is functional coverage, and how is it different from code coverage?
What is UVM, in one paragraph?
What is formal verification, and where is it used?

Physical Design

The layout side.

What are the main steps from netlist to GDSII?
Why is the clock tree built separately from the rest of the routing?
What are IR drop and electromigration?
What's the difference between DRC and LVS?
What is crosstalk?

DFT & Test

Making chips testable.

Why does a chip need to be tested if the design was verified?
What is a scan chain?
What is a stuck-at fault?
What does ATPG do?
What is BIST, and where is it used?

Fabrication & Packaging

How chips are made.

What happens in photolithography?
What is yield, and why do large dies cost more per good die?
What is the difference between wire bonding and flip-chip?
What are chiplets, and why are companies moving to them?
What is a FinFET, and why did it replace planar transistors?

Projects & Fit

The round that decides most fresher offers.

Walk me through your project in two minutes.
What exactly did you do, as opposed to your team?
How did you verify that it worked?
What was the hardest bug, and how did you find it?
Which VLSI domain do you want to work in, and why?

WORKED ANSWERS

18 general VLSI questions, answered the way interviewers expect

Answer out loud first, then open each one. Every answer shows what a strong reply covers, what the interviewer is listening for, and the slip that costs the most.

01Walk me through the ASIC design flow, from specification to tape-out.Foundational

Specification and architecture: what the chip does, its interfaces, performance, power and area targets.
RTL design: the hardware described in Verilog or SystemVerilog.
Verification: simulation, coverage and formal checks that the RTL matches the spec. Runs in parallel with design and takes the most effort.
Synthesis: RTL to a gate-level netlist using a standard-cell library and timing constraints. DFT (scan) is usually inserted here.
Physical design: floorplan, power plan, placement, clock tree, routing.
Signoff: STA across corners, IR drop and EM, DRC, LVS, equivalence checks.
Tape-out: the final layout (GDSII or OASIS) goes to the foundry. Then fabrication, packaging, test and silicon bring-up.

Interviewers listen forVerification and DFT in the right places, and signoff as more than one check.

Common mistakeForgetting verification, or putting the clock tree before placement.

02What are setup and hold time? What happens when each is violated?Foundational

Setup time: how long data must be stable before the clock edge for the flop to capture it reliably.
Hold time: how long data must stay stable after the edge.

A violation of either can make the flop capture the wrong value or go metastable. The fixes differ:

Setup depends on the clock period: shorten the logic path, use faster cells, pipeline, or lower the frequency.
Hold doesn't depend on the period, so slowing the clock never fixes it. Add delay on the short path. A hold failure on silicon can't be fixed at any frequency, which is why hold is checked at every corner.

Interviewers listen for"Hold doesn't depend on frequency."

Common mistakeSaying both are fixed by slowing the clock.

03What are the components of power in CMOS, and how do you reduce each?Foundational

Dynamic (switching): charging and discharging capacitance, αCV²f. Reduce with clock gating (lower α), lower voltage (DVFS), less capacitance (smaller cells, shorter wires) and lower frequency where possible.
Short-circuit: the brief current when both PMOS and NMOS conduct during a transition. Reduce with sharp input transitions.
Static (leakage): current that flows even when nothing switches, mainly subthreshold and gate leakage. Reduce with high-V_t cells off the critical path, power gating idle blocks, and body biasing.

At advanced nodes leakage is a large share of the total, which is why power gating and multi-V_t design matter so much.

Interviewers listen forOne technique per component, and V² as the biggest lever.

Common mistakeSaying CMOS has no static power.

04ASIC or FPGA: what's the difference, and when would you choose each?Foundational

ASIC: custom silicon for one design. Best performance, power and unit cost at volume, but high one-time cost (masks, design effort, months to fabricate) and no changes after tape-out.
FPGA: a reconfigurable chip programmed after manufacture. No mask cost and fast turnaround, but slower, more power-hungry and more expensive per unit.

Choose an ASIC for high volume or tight power and performance (phones, AI accelerators). Choose an FPGA for low volume, prototyping, changing standards, or products that need field updates. Many ASICs are prototyped on FPGAs first.

Interviewers listen forVolume and NRE as the deciding factors.

Common mistake"FPGA is for students, ASIC for industry."

05What's the difference between a latch and a flip-flop? Why do most designs use flip-flops?Foundational

Latch: level-sensitive. While enabled, the output follows the input (transparent).
Flip-flop: edge-triggered. It samples the input only at the clock edge.

Flops make timing simple: each path has one clear launch and capture edge, so static timing analysis is straightforward and races can't pass through. Latches are smaller and allow time borrowing, so they appear in high-performance designs and clock gating cells, but they need careful timing. Unintended latches from incomplete RTL are a classic bug.

Interviewers listen forLevel vs edge, and the timing argument.

Common mistakeNot knowing where latches are still used deliberately.

06How does a CMOS inverter work? Why is the PMOS usually wider?Foundational

A PMOS connects the output to V_DD and an NMOS connects it to ground; both gates are tied to the input. Input low: PMOS on, NMOS off, output high. Input high: NMOS on, PMOS off, output low. In either steady state one transistor is off, so almost no current flows: that's why CMOS uses little static power.

Holes have lower mobility than electrons, so a PMOS of the same size conducts less current. Making the PMOS roughly 2–3 times wider balances rise and fall times and puts the switching threshold near V_DD/2.

Interviewers listen forOne transistor always off, and mobility as the reason.

Common mistakeGiving a fixed ratio without explaining why.

07What is metastability, and how do you deal with it?Applied

If data changes inside a flop's setup-hold window, the flop can hang between 0 and 1 for an unpredictable time before settling. This happens whenever a signal crosses from one clock domain to another, or comes in asynchronously.

Single-bit signals: pass them through two (or more) flops in the receiving domain. The first may go metastable; it gets a full cycle to settle before the second samples it.
Multi-bit data: never synchronise bit by bit. Use a handshake, an asynchronous FIFO with Gray-coded pointers, or a synchronised enable.

It can't be eliminated, only made extremely unlikely; mean time between failures grows exponentially with the settling time you give it.

Interviewers listen for"Reduce, not eliminate", and the multi-bit rule.

Common mistakeUsing a two-flop synchroniser on a data bus.

08Why is a chip tested after manufacturing if the design was verified? What is scan?Applied

Verification proves the design is correct. Manufacturing test checks that each physical chip was built correctly: particles, shorts and opens create defects in individual dies.

Testing every internal flop through the pins would be impossible, so DFT adds scan: in test mode, flops are linked into shift registers (scan chains). A tester shifts in a pattern, runs one functional clock, and shifts the result out. ATPG tools generate patterns that detect modelled faults, such as a node stuck at 0 or 1, and report fault coverage.

Interviewers listen forDesign bugs vs manufacturing defects.

Common mistakeCalling DFT "another kind of verification".

09Why does verification take so much effort, and how is "done" decided?Applied

A bug that reaches silicon can cost a re-spin: new masks and months of delay. Verification has to explore an enormous state space, so most teams spend more engineering effort on it than on design.

Constrained-random stimulus explores combinations no one thought to write.
Self-checking scoreboards and assertions decide pass or fail automatically.
Functional coverage, written from a verification plan, measures which scenarios were actually exercised.

"Done" means the plan is covered: coverage goals met, no open critical bugs, the bug-discovery rate has flattened, and code coverage holes are reviewed. Formal checks are added for blocks where simulation can't reach every case.

Interviewers listen forA plan-driven definition of done.

Common mistake"When all tests pass."

10Name the main low-power techniques and where in the flow each is applied.Applied

Clock gating (RTL and synthesis): stop the clock to idle registers.
Multi-V_t cells (synthesis and PD): low-V_t only where timing needs it, high-V_t elsewhere to cut leakage.
Power gating (architecture, UPF, PD): switch off whole blocks, with isolation cells on outputs and retention flops where state must survive.
Multi-voltage domains (architecture, UPF): run blocks at different supplies, with level shifters between them.
DVFS (system and software): lower voltage and frequency when full performance isn't needed.

The power intent is captured in a UPF file, used consistently from simulation to signoff.

Interviewers listen forIsolation, retention and level shifters with power gating.

Common mistakeTreating clock gating and power gating as the same thing.

11What are AXI, AHB and APB, and where would you use each?Applied

All three are on-chip bus protocols from Arm's AMBA family.

AXI: high-performance. Separate read and write channels, bursts, multiple outstanding transactions and out-of-order completion. Used for CPUs, DMA and memory controllers.
AHB: an older, simpler high-performance bus with pipelined transfers but one transaction at a time per master. Common in microcontrollers.
APB: low-power, low-speed, simple two-phase transfers. Used for configuration registers and peripherals such as UART, timers and GPIO.

A typical SoC uses AXI on the main interconnect and a bridge down to APB for peripheral registers.

Interviewers listen forThe valid/ready handshake and independent channels in AXI.

Common mistakeSaying APB is "slow AXI".

12What does PPA mean, and how would you trade one part against another?Applied

Power, performance and area: the three numbers every design is judged on. Improving one usually costs another.

Pipelining raises frequency (performance) but adds flops (area, power) and latency.
Parallel hardware raises throughput but costs area and leakage.
Lower voltage cuts power sharply but slows the logic.
Resource sharing saves area but adds MUXes and may lengthen the critical path.

The right trade comes from the product: a phone SoC is power-limited, a server chip is often performance-limited, an IoT chip is cost (area) limited.

Interviewers listen forA real example and the product context.

Common mistakeDefining PPA without any trade-off.

13"Walk me through your project." How should you structure the answer?Scenario / debug

Problem, one line: what it does and why it matters.
Architecture, one sketch: the main blocks and interfaces.
Your part: what you personally designed, coded or verified.
How you proved it worked: testbench, test cases, coverage, FPGA or board results.
One real problem: a bug or timing issue, how you found it and what fixed it.
Results and next step: numbers (frequency, resources, throughput) and what you'd change.

Keep the first pass to about two minutes and let the interviewer pull on the parts they're interested in. See the project answer makeover below.

Interviewers listen forOwnership, verification and numbers.

Common mistakeExplaining the textbook protocol instead of what you built.

14After synthesis, your design misses its target frequency by 15%. What do you do?Scenario / debug

Read the timing report: which paths fail, by how much, and do they share a start point, end point or block?
Check constraints first: a missing false path or multicycle path can make a correct design look slow.
Look at the logic: long arithmetic chains, deep MUX or priority logic, high fanout.
Fix in the RTL: pipeline the long path, restructure logic, duplicate high-fanout registers, precompute values a cycle earlier.
Then in implementation: faster cells, better placement, useful skew.

15% is usually an architecture problem, not something a tool option will fix, so be ready to discuss adding a pipeline stage and its latency cost.

Interviewers listen forReport first, constraints second.

Common mistake"Increase the clock period."

15Your design works in simulation but fails on the FPGA board. How do you debug it?Scenario / debug

Timing: did the implementation meet timing with correct constraints for every clock? Unconstrained paths fail silently.
Clocks and resets: is the PLL locked, is reset held long enough and released synchronously, are clocks used as data or generated from logic?
Asynchronous inputs: buttons and external signals need synchronisers and debouncing.
Pins and I/O standards: wrong pin assignments or voltage standards.
Simulation coverage: the simulation may never have exercised what the board does (real data, long runs, back-to-back input).

Then probe internal signals with an integrated logic analyser and compare against simulation.

Interviewers listen forConstraints, clocks and async inputs before anything else.

Common mistakeAssuming the FPGA or the tool is broken.

16First silicon is back and many chips fail test. How would the team investigate?Scenario / debug

Characterise the failures: which tests fail, on what share of dies, and at which voltage and temperature.
Pattern on the wafer: failures clustered at the edge or in one region suggest a process issue; random failures suggest defects or marginal design.
Shmoo plots: pass/fail across voltage and frequency show whether it's a timing margin problem.
Scan diagnosis: failing scan patterns point to likely defect locations for physical failure analysis.
Design bug? If every die fails the same way, it's likely functional: reproduce it in simulation or emulation and plan a fix (software workaround, metal ECO or re-spin).

Interviewers listen forSeparating manufacturing defects from design bugs.

Common mistakeJumping to "redesign the chip".

17The interviewer asks about something you've never studied. What do you do?Scenario / debug

Say so honestly: "I haven't worked with that directly."
Connect it to what you know: "I'd expect it to work like… because…"
Reason aloud: interviewers often care more about how you think than whether you know the term.
Ask a short clarifying question if the question itself is unclear.

Never bluff. A wrong answer delivered confidently does more damage than "I don't know, but here's how I'd find out."

Interviewers listen forHonesty and structured reasoning.

Common mistakeInventing an answer and defending it.

18"Why this company?" How do you prepare a real answer?Scenario / debug

What they build: their main products and the kinds of chips or tools behind them (CPUs, GPUs, mobile SoCs, analog, EDA software).
Where your role fits: which part of that work the role touches, and what the job description emphasises.
Recent news: a new product, process, or acquisition you can mention accurately.
Your link: a project, course or interest that connects to their work.

Then prepare a few technical topics that company is known for. Our company interview guides describe what common rounds focus on.

Interviewers listen forSpecific, accurate knowledge and a genuine link.

Common mistake"It's a big company with good growth."

SOLVED NUMERICALS

8 VLSI numericals, solved step by step

These come up in written tests and as quick checks during interviews. Solve each on paper, then tap to check.

N1 · DYNAMIC POWERBEGINNERα = 0.15, switched capacitance 2 nF, V_DD = 0.9 V, f = 1 GHz. Find the dynamic power, and the saving if V_DD drops to 0.8 V.Show solution ↓

P = 0.15 × 2e-9 × 0.9² × 1e9 = 0.243 W
P' = 0.15 × 2e-9 × 0.8² × 1e9 = 0.192 W
Saving = 1 − (0.8/0.9)² ≈ 21%

Note: an 11% voltage cut gives a 21% power cut, because power goes with V².

N2 · SETUP SLACKBEGINNERT = 2 ns, t_cq = 0.15 ns, logic = 1.5 ns, t_su = 0.1 ns, uncertainty 0.05 ns, no skew. Find the slack and f_max.Show solution ↓

Required = 2 − 0.1 − 0.05 = 1.85 ns
Arrival  = 0.15 + 1.5   = 1.65 ns
Slack    = 1.85 − 1.65  = +0.20 ns
T_min = 1.65 + 0.1 + 0.05 = 1.8 ns → f_max ≈ 556 MHz

N3 · HOLD CHECKINTERMEDIATEt_cq = 0.10 ns, shortest logic 0.02 ns, t_h = 0.05 ns, capture clock 0.10 ns later than launch. Is hold met? How much delay is needed?Show solution ↓

Arrival  = 0.10 + 0.02 = 0.12 ns
Required = 0.05 + 0.10 = 0.15 ns
Slack    = 0.12 − 0.15 = −0.03 ns → violation
Add at least 30 ps on the data path

Note: the clock period never appears; slowing the clock won't help.

N4 · DIES & YIELDINTERMEDIATE300 mm wafer, 150 mm² die, D₀ = 0.2 defects/cm², wafer cost $9,000. Find gross dies, Poisson yield and cost per good die.Show solution ↓

Gross = π·150²/150 − π·300/√300
      = 471.2 − 54.4 ≈ 416 dies
Yield = e^(−0.2 × 1.5) = e^(−0.3) ≈ 74.1%
Good  ≈ 416 × 0.741 ≈ 308
Cost  = 9000 / 308 ≈ $29 per good die

Note: A must be in cm² for the yield formula: 150 mm² = 1.5 cm².

N5 · MOORE'S LAWBEGINNERA chip has 2 billion transistors. If counts double every two years, how many would a chip have ten years later?Show solution ↓

Doublings = 10 / 2 = 5
Factor    = 2^5 = 32
Count     = 2 B × 32 = 64 billion

Note: the pace has slowed at recent nodes; growth now comes from bigger dies and chiplets as well as density.

N6 · K-MAPBEGINNERSimplify F(A,B,C,D) = Σm(0, 2, 5, 7, 8, 10, 13, 15).Show solution ↓

B=0, D=0 : m0, m2, m8, m10  → B'D'
B=1, D=1 : m5, m7, m13, m15 → BD
F = B'D' + BD = B XNOR D

Note: A and C drop out completely; the four corners of the K-map form one group.

N7 · IR DROPBEGINNERA block draws 1 W at 0.9 V through a grid with 25 mΩ effective resistance. Find the drop and whether it fits a 5% budget.Show solution ↓

I  = 1 / 0.9 ≈ 1.11 A
ΔV = 1.11 × 0.025 ≈ 27.8 mV
27.8 / 900 ≈ 3.1% → within a 5% budget

N8 · SCAN TEST TIMEINTERMEDIATE10,000 scan flops in 10 balanced chains, 2,000 patterns, shift clock 50 MHz. Roughly how long does the scan test take?Show solution ↓

Chain length = 10,000 / 10 = 1,000
Cycles ≈ 2,000 × (1,000 + 1) + 1,000 ≈ 2,003,000
Time   ≈ 2,003,000 / 50 MHz ≈ 40 ms

Note: more chains (or scan compression) shorten every pattern, which is why test time drops sharply with compression.

PROJECT ANSWER MAKEOVER

Rebuild a weak "tell me about your project" answer

Most fresher interviews turn on this question. Here's a typical answer, the five things wrong with it, and what a strong version sounds like.

Q: Tell me about your final-year project.

A: My project was a UART. UART is a serial communication     (1)
   protocol used in many devices. We used Verilog and
   Xilinx Vivado. Our team of 4 did RTL and simulation.     (2)
   It worked successfully on the FPGA board.                (3)
   We learned a lot about digital design and teamwork.     (4)

Q: What baud rate, and how did you generate it?

A: 9600… I think the tool handled it.                       (5)

Defines the protocol instead of describing what was built. The interviewer knows what a UART is.
"Our team": no idea what this candidate did personally.
No evidence: how was it verified, which tests, what did "worked" mean?
A generic ending that says nothing about engineering decisions or results.
Can't explain a core detail of their own design. This is the line that loses the offer.

What does a strong two-minute version sound like?

"I built a UART transmitter and receiver in Verilog on an FPGA board, for a sensor that sends data to a PC. I wrote the receiver: a baud-rate generator with 16× oversampling, a start-bit detector that samples mid-bit, and an FSM for the data and stop bits, with a framing-error flag. I verified it with a self-checking testbench that looped the transmitter into the receiver over 10,000 random bytes, including back-to-back frames, then on the board at 9600 and 115200 baud against a PC terminal. The hardest bug was an occasional corrupted byte on the board that never appeared in simulation: the receive pin went straight into the FSM without a synchroniser, and adding a two-flop synchroniser fixed it. It used about 120 LUTs and met timing at the board's 50 MHz clock. Next I'd add a FIFO and parity."

How is the baud divisor actually worked out?

For a 50 MHz clock, 16× oversampling and 9600 baud: 50,000,000 / (16 × 9600) ≈ 325.5, rounded to 326. The real rate is 50,000,000 / (16 × 326) ≈ 9586 baud, an error of about −0.15%, well inside the couple of percent a UART tolerates. Being able to do this on the spot is exactly what the follow-up was testing.

Which follow-ups should you expect?

Why sample in the middle of the bit? What happens if the two clocks differ by 3%? How did you handle a stop bit that's 0? What would change for a 1 Mbaud link? How did you test framing errors? Prepare a short, specific answer for each.

How do I prepare my own project like this?

Write the six-part structure from worked answer 13, add real numbers, and list ten likely follow-ups with answers. Say it aloud, timed, until it fits in two minutes. The ebook has 280 project questions across RTL, verification, PD, DFT and FPGA to practise against.

RAPID-FIRE ROUND

20 quick questions, one-line answers

Screening calls often open like this. Answer each in a few seconds, then tap to check.

What does VLSI stand for?

Very Large Scale Integration.

Universal gates?

NAND and NOR.

Latch or flop: which is edge-triggered?

Flip-flop.

Flops for a mod-10 counter?

Dynamic power formula?

αCV²f.

Which carrier is faster: electrons or holes?

Electrons.

Does slowing the clock fix hold?

No.

Standard fix for a single-bit CDC?

A two-flop synchroniser.

What does synthesis produce?

A gate-level netlist.

Final layout file format?

GDSII (or OASIS).

DRC checks what?

Layout against the foundry's geometry rules.

LVS checks what?

Layout connectivity against the netlist.

What does a scan chain turn flops into?

A shift register, in test mode.

Most common fault model?

Stuck-at (0 or 1).

Main verification methodology?

UVM.

What does UPF describe?

Power intent: domains, switches, isolation, retention.

PVT stands for?

Process, voltage, temperature.

Which bus is used for peripheral registers?

APB.

What does tape-out mean?

Sending the final layout to the foundry.

What limits yield on large dies?

Defect density: yield falls exponentially with area.

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