RTL design interview questions, with Verilog answers, solved problems and a real code review

Blocking (=) updates the variable immediately, so the next statement sees the new value. Non-blocking (<=) evaluates every right-hand side first and updates all left-hand sides together at the end of the time step, which is how flip-flops behave on a clock edge.

// Non-blocking: a real 2-stage shift register
always @(posedge clk) begin
  q1 <= d;
  q2 <= q1;   // old q1
end

// Blocking: q2 gets d in the same cycle, one flop disappears
always @(posedge clk) begin
  q1 = d;
  q2 = q1;    // new q1
end

Rule: <= in clocked blocks, = in combinational blocks, and never mix the two on the same variable.

always @(*)
  if (sel) y = a;     // no else: y must hold its value

When sel is 0, nothing assigns y, so it has to remember its last value. Remembering without a clock is a latch. Fix it by assigning the output on every path, most simply with a default at the top:

always @(*) begin
  y = b;              // default
  if (sel) y = a;
end

The same applies to a case without a default and to any output assigned in only some branches.

• Synchronous: reset only acts on a clock edge. Glitch-tolerant and simple for timing, but needs a running clock and adds logic to the data path.
• Asynchronous: acts immediately, works without a clock, and keeps the data path clean, but its release is a timing event; if it's released near a clock edge, flops can go metastable or come out of reset in different cycles.

The common answer: assert asynchronously, deassert synchronously, with a reset synchroniser per clock domain:

always @(posedge clk or negedge rst_n_in)
  if (!rst_n_in) {r2, r1} <= 2'b00;
  else           {r2, r1} <= {r1, 1'b1};
assign rst_n = r2;   // use this everywhere in the domain

• Moore: outputs depend only on the current state. Outputs are stable for the whole cycle and easy to register, but the machine reacts one cycle later and may need more states.
• Mealy: outputs depend on the state and the current inputs. It reacts in the same cycle and often needs fewer states, but input glitches pass straight to the output and the path from input to output is combinational.

Choice: Moore (or a Mealy with registered outputs) when outputs leave the block or drive control signals; Mealy when a one-cycle response matters and the outputs stay inside a timed, synchronous path.

An if / else if chain has priority: the first true condition wins, so synthesis builds a chain of MUXes where the last branch passes through every stage. A case on one select signal with exclusive items describes a parallel MUX, which is usually faster and smaller.

// Priority: req[0] wins over req[1] over req[2]
always @(*)
  if      (req[0]) gnt = 3'b001;
  else if (req[1]) gnt = 3'b010;
  else if (req[2]) gnt = 3'b100;
  else             gnt = 3'b000;

Use priority only when the specification has it. Avoid full_case and parallel_case pragmas: they change what synthesis builds without changing what simulation does.

An enable flop keeps the clock running and uses a MUX to feed back the old value. A gated clock stops the clock to the register, saving the clock and flop switching power that the enable flop still burns.

// Enable: clock always toggles
always @(posedge clk) if (en) q <= d;

// Never gate with a plain AND in RTL: glitches when en changes
// assign gclk = clk & en;   // don't
// Use the library's integrated clock-gating (ICG) cell,
// or let synthesis insert it from the enable above.

Clock gating pays off for wide registers (a bank of 32 or more bits) that are idle often. The ICG holds the enable in a latch while the clock is high, so the gated clock can't glitch.

Use pointers one bit wider than the address. Equal pointers mean empty; equal addresses with different MSBs mean the write pointer has lapped the read pointer, so the FIFO is full.

module sync_fifo #(parameter W = 8, AW = 4) (
  input              clk, rst_n, wr, rd,
  input      [W-1:0] din,
  output     [W-1:0] dout,
  output             full, empty);

  reg [W-1:0] mem [0:(1<<AW)-1];
  reg [AW:0]  wp, rp;               // one extra bit

  assign empty = (wp == rp);
  assign full  = (wp[AW] != rp[AW]) && (wp[AW-1:0] == rp[AW-1:0]);
  assign dout  = mem[rp[AW-1:0]];

  always @(posedge clk or negedge rst_n)
    if (!rst_n) begin wp <= 0; rp <= 0; end
    else begin
      if (wr && !full)  begin mem[wp[AW-1:0]] <= din; wp <= wp + 1; end
      if (rd && !empty) rp <= rp + 1;
    end
endmodule

Then say what you'd add: a registered dout for RAM inference, overflow and underflow flags, and a test with simultaneous read and write when full and when empty.

reg in_d;
always @(posedge clk or negedge rst_n)
  if (!rst_n) in_d <= 1'b0;
  else        in_d <= in;

assign rise = in & ~in_d;     // falling: ~in & in_d, any: in ^ in_d

If in comes from another clock domain or a pin, synchronise it with two flops first and detect the edge on the synchronised copy; otherwise the pulse can be lost or doubled. For a glitch-free registered output, register rise as well, at the cost of one cycle.

A mod-3 counter gives a 1/3 duty output. Make a copy of that output shifted by half an input period on the falling edge, and OR the two: the result is high for 1.5 of 3 input cycles.

reg [1:0] cnt;
reg       p, n;
always @(posedge clk or negedge rst_n)
  if (!rst_n) cnt <= 0;
  else        cnt <= (cnt == 2) ? 0 : cnt + 1;

always @(posedge clk or negedge rst_n)
  if (!rst_n) p <= 0; else p <= (cnt == 0);   // high 1 of 3

always @(negedge clk or negedge rst_n)
  if (!rst_n) n <= 0; else n <= p;            // shifted half a cycle

assign clk_div3 = p | n;                       // high 1.5 of 3

Mention that in a real chip this output would come from a PLL or a library divider cell and be defined to STA as a generated clock; in most RTL, a clock enable that pulses every third cycle is the better choice.

Keep a pointer to the last winner. On each cycle, search for the first request after that pointer, wrapping around, and grant it. That way every requester gets a turn and nobody starves.

reg [1:0] last;                         // last granted index
integer   i;
reg [1:0] idx;
always @(*) begin
  gnt = 4'b0;
  for (i = 1; i <= 4; i = i + 1) begin
    idx = last + i;                     // wraps naturally in 2 bits
    if (req[idx] && gnt == 4'b0) gnt[idx] = 1'b1;
  end
end
always @(posedge clk or negedge rst_n)
  if (!rst_n)     last <= 2'd3;          // so requester 0 goes first
  else if (|gnt)  last <= (gnt[1] ? 2'd1 : gnt[2] ? 2'd2 : gnt[3] ? 2'd3 : 2'd0);

For many requesters, mention the faster masked-priority version: mask off requests at or below the last winner, take the lowest set bit with x & -x, and fall back to the unmasked request if the masked one is empty.

The cleanest style separates the state register from the next-state logic, with outputs either decoded from the state (Moore) or registered:

localparam IDLE = 2'd0, RUN = 2'd1, DONE = 2'd2;
reg [1:0] st, nx;

always @(posedge clk or negedge rst_n)
  if (!rst_n) st <= IDLE; else st <= nx;

always @(*) begin
  nx = st;                                   // default: stay
  case (st)
    IDLE: if (start) nx = RUN;
    RUN:  if (last)  nx = DONE;
    DONE:            nx = IDLE;
    default:         nx = IDLE;              // recover from illegal states
  endcase
end

• Binary: fewest flops, more decode logic. Good for ASICs with many states.
• One-hot: one flop per state, very shallow next-state logic. Popular on FPGAs where flops are plentiful.
• Gray: one bit changes per transition, useful when transitions are mostly sequential or the state is observed across domains.

A two-flop synchroniser alone can miss it: the slow clock may never sample a pulse shorter than its own period. Convert the pulse to a level change first, synchronise the level, then detect its edge on the other side.

// fast domain: toggle on each pulse
always @(posedge clk_f or negedge rst_f_n)
  if (!rst_f_n) t <= 1'b0; else if (pulse_f) t <= ~t;

// slow domain: synchronise, then edge-detect
always @(posedge clk_s or negedge rst_s_n)
  if (!rst_s_n) {s3, s2, s1} <= 3'b0;
  else          {s3, s2, s1} <= {s2, s1, t};
assign pulse_s = s3 ^ s2;

The limit: pulses must be spaced far enough apart (a few slow-clock periods) or toggles merge. If they can arrive back to back, use a handshake or an async FIFO.

1. Simulation-synthesis mismatch in the RTL: incomplete sensitivity lists, blocking assignments in clocked blocks, full_case/parallel_case pragmas, initial blocks or # delays the design relied on.
2. X handling: RTL if (x) takes the else branch and hides unknowns; gates propagate X. Look for uninitialised registers without reset.
3. Timing: with SDF annotation, failures can be real setup or hold violations, or unsynchronised CDC paths that only fail with real delays.
4. Testbench: driving inputs exactly on the clock edge works in RTL and races in gates. Drive them away from the active edge.

Run lint and logic equivalence (RTL vs netlist) to separate a coding problem from a timing problem quickly.

• Find the real path first: read the timing report. Is it a long arithmetic chain, a wide MUX, a priority chain, or a high-fanout control signal?
• Pipeline: add a register stage in the middle of the long path and adjust the control to match the added latency.
• Restructure: turn priority chains into parallel logic, balance adder trees, precompute values a cycle earlier, move late-arriving signals closer to the output.
• Reduce fanout: duplicate a register that drives hundreds of loads.
• Check the constraint: is it actually a multicycle or false path that was never constrained?

Then say the cost: extra latency, area, or a protocol change for the blocks around yours.

Synchronising each bit separately doesn't work: bits resolve independently, so for one cycle the receiver can see some old bits and some new bits, a value that never existed.

• Handshake (req/ack): hold the data stable, synchronise a single control bit, sample the bus once it's seen. Simple; good for occasional transfers.
• MUX recirculation: synchronise a "data valid" bit and use it to load the bus into a destination register.
• Async FIFO: for streaming data. Gray-coded pointers cross the domains, data stays in the memory.
• Gray code: only for values that change by one step, like counters.

Finish with how you'd prove it: a CDC tool run and an assertion that the bus is stable while the control bit crosses.

1. Trace the driver: in the waveform, follow the X back to the first signal that went X.
2. Reset: is reset asserted at all, with the right polarity, for long enough, and does that register have a reset branch?
3. Multiple drivers: two assigns or always blocks driving one net give X when they disagree.
4. Unconnected or mis-sized ports: a floating input reads Z, which becomes X in logic; check width-mismatch warnings.
5. Loops: a combinational loop or a register that only ever loads itself never leaves X.

Lint warnings usually point straight at the cause, so read them before stepping through waves.

• Area by hierarchy: find which submodule grew, then read its inferred resources.
• Widths: 32-bit integers used for small counters, products wider than needed, sums that never get truncated.
• Memories built from flops: an array with an asynchronous read or a reset won't map to RAM.
• Unrolled loops and duplicated arithmetic: a multiplier in each branch where one shared multiplier would do.
• Over-constrained timing: tight constraints make synthesis upsize cells and duplicate logic.

1. Map the interfaces: ports, clocks, resets and which domain each signal belongs to.
2. Run lint and CDC: they show unsafe crossings, latches and width problems before you touch anything.
3. Find the state: FSMs, counters and memories; draw a block diagram from them.
4. Get a baseline: an existing test or a quick testbench that passes before your change.
5. Change small, re-check often: one change at a time, rerun the tests and lint, and document what you learned.