AV
Avnita
Design Verification Mentor
BEST FORFreshers and students moving into verification
Helps you get the SystemVerilog fundamentals right before your first DV round. Expect to explain OOP with classes, randomisation and interfaces, then put together a small self-checking testbench while talking through each choice.
IN YOUR MOCK INTERVIEW- Classes, handles and inheritance
- Constraints and randomisation
- A small self-checking testbench
A QUESTION YOU MIGHT HEAR“You copy a class handle and change a field through the copy. What happens to the original, and why?”
SystemVerilogOOPFresher DV
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SO
Sonia
UVM Verification Mentor
BEST FORVerification engineers with 1–5 years' experience
Interviews you the way UVM-heavy teams do. The questions start from your own testbench: how it is structured, why your sequences look the way they do, how you use the factory and config_db, and how you trace a failing test back to its cause.
IN YOUR MOCK INTERVIEW- Testbench architecture you can defend
- Sequences and virtual sequences
- Debugging a failing regression
A QUESTION YOU MIGHT HEAR“A test passes on its own but fails in regression. How would you use UVM to find out why?”
UVMSequencesFactory & config_db
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PR
Priyanka
SVA & Coverage Mentor
BEST FORDV candidates preparing for deep-dive rounds
Goes deep on the topics that separate strong DV candidates from average ones. You will write and reason about assertions on the spot, plan functional coverage for a feature, and explain how you would steer constrained-random stimulus to close the holes.
IN YOUR MOCK INTERVIEW- Writing SVA under pressure
- Planning functional coverage
- Closing coverage holes
A QUESTION YOU MIGHT HEAR“Write an assertion that checks every request is acknowledged within three to five cycles.”
SVAFunctional coverageConstrained-random
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NI
Nitin
Synthesis, Low Power & STA Mentor
BEST FORFront-end and implementation roles where synthesis and timing are tested
Covers the bridge between RTL and layout. Expect questions on synthesis constraints and QoR, low-power techniques such as clock gating, multi-Vt cells and power domains, and reading a timing report to decide how to fix setup and hold.
IN YOUR MOCK INTERVIEW- SDC constraints and synthesis QoR
- Clock gating, multi-Vt and power domains
- Reading and fixing timing reports
A QUESTION YOU MIGHT HEAR“Synthesis meets timing, but the post-layout netlist fails setup. What do you look at first?”
SynthesisLow powerSTA
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BEST FORMid-to-senior engineers switching roles or companies
Tests how you think as a designer. The round moves from datapath and pipeline choices to meeting timing on an FPGA, and the follow-ups keep pushing until you have to defend each trade-off you made.
IN YOUR MOCK INTERVIEW- Datapath and pipeline design
- Meeting timing on an FPGA
- Defending design trade-offs
A QUESTION YOU MIGHT HEAR“Design a FIFO that crosses two clock domains. How do you size it, and why?”
RTLFPGAMicro-architecture
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AN
Ananya
Physical Design Mentor
BEST FORPhysical design and STA candidates, freshers to switchers
Builds the round around real implementation problems: planning a floorplan, making CTS decisions, fixing congestion and IR drop, and working out why a path fails setup or hold at a particular corner.
IN YOUR MOCK INTERVIEW- Floorplan and macro placement
- CTS and congestion fixes
- Setup and hold across corners
A QUESTION YOU MIGHT HEAR“After placement there is a congestion hotspot next to a macro. Walk me through how you fix it.”
Physical designSTACTS
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