The VLSI glossary: every term, in plain language

A

Antenna effect Physical design

Charge that builds up on long metal wires during plasma etching and can damage the thin gate oxide it connects to. Fixed with antenna diodes or by jumping to a higher metal layer.

Arbiter RTL & HDL

Logic that decides which of several requesters gets a shared resource. Common schemes are fixed priority and round-robin.

ASIC Industry

Application-specific integrated circuit: a chip designed for one purpose and manufactured as custom silicon, as opposed to a reprogrammable FPGA.

Assertion (SVA) Verification

A property checked automatically during simulation or proved formally, e.g. "every request gets a grant within 4 cycles". Written in SystemVerilog Assertions.

Async FIFO RTL & HDL

A FIFO whose write and read sides use different clocks. The pointers cross clock domains in Gray code so only one bit changes at a time.

ATPG Test (DFT)

Automatic test pattern generation: software that creates the input patterns and expected outputs used to detect manufacturing faults on a tester.

AXI RTL & HDL

Arm's high-performance on-chip bus protocol (part of AMBA), with separate read/write address, data and response channels and a valid/ready handshake.

B

Back-end Industry

The physical half of chip design: floorplanning, placement, clock tree, routing and sign-off. The front-end is RTL design and verification.

Bandgap reference Analog & devices

An analog circuit that produces a stable reference voltage (about 1.2 V) that barely changes with temperature or supply.

BIST Test (DFT)

Built-in self-test: on-chip logic that tests part of the chip itself. MBIST tests memories, and LBIST tests logic.

Blocking assignment RTL & HDL

The = assignment in Verilog procedural code. It executes immediately, in order, and is used for combinational logic.

Bond wire Fab & packaging

A fine gold or copper wire that connects a pad on the die to the package lead in wire-bonded packages.

Boundary scan (JTAG) Test (DFT)

A chain of test cells around a chip's I/O pins, controlled through the IEEE 1149.1 JTAG port, used to test board connections and access on-chip debug.

C

Chiplet Fab & packaging

A smaller die designed to be combined with others in one package, instead of building one huge monolithic die.

Clock domain crossing (CDC) RTL & HDL

Any signal passing between logic running on unrelated clocks. It needs synchronizers or handshakes to avoid metastability and data loss.

Clock gating Low power

Turning off the clock to idle registers to save dynamic power, usually with an integrated clock-gating (ICG) cell to avoid glitches.

Clock jitter Timing

Cycle-to-cycle variation in when a clock edge arrives, caused by the clock source and noise. It's modelled in STA as part of clock uncertainty.

Clock skew Timing

The difference in clock arrival time between two flip-flops. It can help or hurt setup and hold depending on its direction.

CMOS Analog & devices

Complementary metal-oxide-semiconductor: the technology behind nearly all digital chips, pairing PMOS pull-up and NMOS pull-down networks.

Code coverage Verification

A measure of which lines, branches, conditions, toggles and FSM states the tests exercised. It's necessary but not sufficient for verification sign-off.

Combinational logic Digital logic

Logic whose outputs depend only on the current inputs, with no memory: gates, multiplexers, adders.

Constrained-random verification Verification

Generating random stimulus within legal limits (constraints) so tests hit cases no one thought to write by hand.

Corner (PVT) Timing

A combination of process, voltage and temperature at which timing and power are analysed, e.g. slow-slow, 0.72 V, 125 °C.

Coverage closure Verification

The process of analysing coverage holes and adding tests or fixing constraints until the verification plan's coverage goals are met.

Critical path Timing

The path with the worst (smallest) slack. It sets the maximum clock frequency of the design.

Crosstalk Physical design

Unwanted coupling between neighbouring wires that can add delay or glitches to a victim net. It's analysed as part of signal integrity.

CRPR Timing

Clock reconvergence pessimism removal: removing the false pessimism of derating the shared part of the launch and capture clock paths differently.

CTS Physical design

Clock tree synthesis: building a buffered clock network that delivers the clock to every flop with low skew and controlled transition.

D

Decap cell Physical design

A decoupling capacitor cell placed near switching logic to supply bursts of current and reduce dynamic IR drop.

Design rule check (DRC) Physical design

Checking that layout geometry obeys the foundry's manufacturing rules: widths, spacings, enclosures, densities.

DFT Test (DFT)

Design for testability: adding structures such as scan chains, BIST and compression so every manufactured chip can be tested quickly.

Die Fab & packaging

One individual chip cut from a processed wafer, before it's packaged.

Driver (UVM) Verification

The UVM component that takes transactions from the sequencer and drives them onto the DUT's interface signals.

DUT Verification

Design under test: the RTL block that a testbench is verifying.

DVFS Low power

Dynamic voltage and frequency scaling: lowering voltage and clock speed when full performance isn't needed, to save power.

E

ECO Physical design

Engineering change order: a small, targeted change to a netlist or layout late in the flow, without rerunning everything.

EDA Industry

Electronic design automation: the software used to design chips, from simulators and synthesis to place-and-route and sign-off.

Electromigration (EM) Physical design

Gradual movement of metal atoms under high current density, which eventually causes opens or shorts. Prevented with wider wires and more vias.

F

Fabless Industry

A chip company that designs chips but outsources manufacturing to a foundry. Qualcomm, NVIDIA and MediaTek are examples.

False path Timing

A timing path that can never be exercised in real operation, so it's excluded from timing analysis.

Fault coverage Test (DFT)

The percentage of modelled faults that the test patterns detect.

FinFET Analog & devices

A 3D transistor in which the gate wraps around a thin vertical fin, giving better control than planar transistors. It was used from about 22/16 nm down to 3 nm.

Flip-flop Digital logic

An edge-triggered storage element that captures its input on a clock edge. It's the basic register of synchronous design.

Floorplan Physical design

The first physical design step: setting the die size, placing macros and I/Os, and planning the power grid.

Formal verification Verification

Mathematically proving that properties hold for all possible inputs, rather than simulating selected ones. Also used for equivalence checking.

Foundry Industry

A company that manufactures chips designed by others, such as TSMC, Samsung Foundry, GlobalFoundries or UMC.

FPGA Industry

Field-programmable gate array: a chip of configurable logic blocks and routing that can be reprogrammed to implement any digital design.

FSM Digital logic

Finite state machine: logic that moves between a fixed set of states based on inputs. It comes in Moore and Mealy styles.

Functional coverage Verification

User-defined coverage (covergroups) that measures whether the important features and scenarios from the verification plan were exercised.

G

Gate-all-around (GAA) Analog & devices

The transistor structure after FinFET, in which the gate surrounds stacked nanosheets on all sides. Used at about the 2–3 nm class.

Gate-level simulation (GLS) Verification

Simulating the synthesized netlist, often with timing annotation, to catch issues RTL simulation misses, such as X-propagation and reset problems.

GDSII / OASIS Physical design

The file formats for final chip layout, sent to the foundry at tape-out.

Glitch Digital logic

A short, unwanted pulse on a signal caused by unequal path delays. Dangerous on clocks and asynchronous resets.

Gray code Digital logic

A binary sequence in which consecutive values differ by exactly one bit. Used for CDC pointers and rotary encoders.

H

Hold time Timing

The minimum time data must stay stable after the clock edge. Violations don't depend on the clock period.

I

IP (silicon IP) Industry

A reusable, pre-designed block licensed for use in chips, such as a CPU core, a USB PHY or a memory controller.

IR drop Physical design

The voltage lost across the resistance of the power grid. It slows cells down and can cause timing failures.

L

Latch Digital logic

A level-sensitive storage element that is transparent while enabled. Often inferred by accident in RTL.

Latch-up Analog & devices

A parasitic PNPN structure turning on and shorting the supply rails in CMOS. Prevented by well taps and guard rings.

Layout versus schematic (LVS) Physical design

Checking that the layout's extracted connectivity matches the intended netlist or schematic.

Leakage power Low power

Power consumed even when transistors aren't switching. It's significant at advanced nodes, and reduced with high-Vt cells and power gating.

Level shifter Low power

A cell that translates a signal between two voltage domains.

Linting RTL & HDL

Static checking of RTL for coding problems (latches, width mismatches, multiple drivers) before simulation.

Low-power design Low power

Techniques that reduce dynamic and leakage power: clock gating, power gating, multi-Vt cells, DVFS and multiple voltage domains.

M

Macro Physical design

A large pre-designed block (memory, analog IP, PHY) placed as a single unit during floorplanning.

MBIST Test (DFT)

Memory built-in self-test: on-chip logic that runs algorithmic patterns, such as March tests, on embedded memories.

Mealy machine Digital logic

An FSM whose outputs depend on both the current state and the current inputs.

Metastability Digital logic

An unstable in-between state a flip-flop can enter if its input changes too close to the clock edge. It takes an unpredictable time to resolve.

MMMC Timing

Multi-mode multi-corner: analysing timing across every operating mode and PVT corner at once.

Monitor (UVM) Verification

A passive UVM component that watches interface signals, rebuilds transactions and broadcasts them to scoreboards and coverage.

Moore machine Digital logic

An FSM whose outputs depend only on the current state.

Moore's law Industry

The observation that transistor counts roughly double every couple of years. It has slowed, but it still drives the industry's roadmap.

Multicycle path Timing

A path intentionally given more than one clock cycle to settle, declared in the timing constraints.

N

Netlist RTL & HDL

A description of a circuit as instances of cells and the wires connecting them, typically produced by synthesis.

Node (process node) Fab & packaging

A foundry's process generation, e.g. 7 nm or 3 nm. It's now a marketing name rather than a literal feature size.

Non-blocking assignment RTL & HDL

The <= assignment in Verilog. Every right-hand side is sampled first and updated together, which models flip-flops correctly.

O

OCV Timing

On-chip variation: differences between identical cells on the same die. It's modelled in STA with derates (OCV, AOCV, POCV/SOCV).

Op-amp Analog & devices

An operational amplifier: a high-gain differential amplifier used with feedback in filters, references, regulators and data converters.

OSAT Fab & packaging

Outsourced semiconductor assembly and test: companies that package and test chips, such as ASE and Amkor.

P

Phase margin Analog & devices

How far a feedback loop is from oscillating, measured in degrees at unity gain. Low phase margin causes ringing.

Placement Physical design

Deciding where every standard cell sits in the core area, while optimizing timing, congestion and wirelength.

PLL Analog & devices

Phase-locked loop: a circuit that multiplies and cleans a reference clock to generate on-chip clocks.

Post-silicon validation Industry

Testing real chips in the lab after fabrication to find bugs and characterize behaviour that pre-silicon verification missed.

Power gating Low power

Switching off the supply to idle blocks using header or footer switches to eliminate leakage. Needs isolation and retention.

Power intent (UPF) Low power

A description of a design's power domains, supplies, isolation and retention in the Unified Power Format (IEEE 1801).

Process variation Fab & packaging

Differences in transistor behaviour caused by manufacturing, both die-to-die and within a die.

R

Race condition RTL & HDL

A simulation result that depends on the order the simulator happens to evaluate events. Usually caused by mixing blocking and non-blocking assignments.

RAL (UVM) Verification

Register abstraction layer: a model of a design's registers used to read, write and check them by name in UVM testbenches.

Recovery / removal Timing

The timing checks for de-asserting an asynchronous reset or set relative to the clock. They're the async equivalents of setup and hold.

Regression Verification

Running the full set of tests (often thousands of seeds) regularly to catch new bugs and track progress.

Retention register Low power

A flip-flop that keeps its state in a low-leakage latch while its domain is powered down.

Routing Physical design

Creating the metal wires and vias that connect all the placed cells according to the netlist.

RTL RTL & HDL

Register-transfer level: describing hardware as data moving between registers each clock cycle. It's the level Verilog and VHDL design code is written at.

S

Scan chain Test (DFT)

Flip-flops connected into a shift register in test mode so internal state can be loaded and read out.

Scoreboard Verification

The testbench component that compares the DUT's actual outputs against expected results from a reference model.

SDC Timing

Synopsys Design Constraints: the TCL-based format for timing constraints (clocks, I/O delays, exceptions) used across tools.

Sequence (UVM) Verification

A UVM object that generates a stream of transactions, which is the stimulus scenario itself.

Sequencer (UVM) Verification

The UVM component that arbitrates between sequences and passes their items to the driver.

Sequential logic Digital logic

Logic with memory, whose outputs depend on past inputs through stored state in flip-flops or latches.

Setup time Timing

The minimum time data must be stable before the clock edge. Violations limit the maximum frequency.

Sign-off Physical design

The final set of checks (timing, power, IR/EM, DRC, LVS) that must pass before tape-out.

Slack Timing

Required time minus arrival time for a timing path. Positive slack means it meets timing; negative means it fails.

SoC Industry

System on chip: a single chip integrating CPUs, GPUs, memory controllers, I/O and accelerators.

SPICE Analog & devices

The family of transistor-level circuit simulators used to design and verify analog and custom circuits.

STA Timing

Static timing analysis: checking every timing path against its constraints without simulation vectors.

Standard cell Physical design

A pre-designed, pre-characterized logic cell (NAND, flop, buffer) from a library, placed and routed automatically.

Stuck-at fault Test (DFT)

A fault model in which a net is permanently stuck at 0 or 1. It's the baseline model for ATPG.

Synchronizer Digital logic

Two or more flip-flops in series in the receiving clock domain, giving a metastable signal time to resolve before it's used.

Synthesis RTL & HDL

Converting RTL into a gate-level netlist of standard cells that meets timing, area and power targets.

T

Tape-out Industry

Sending the final layout (GDSII/OASIS) to the foundry for manufacturing. It's the milestone every chip project works towards.

Testbench Verification

The verification environment around a DUT that generates stimulus, checks responses and measures coverage.

Threshold voltage (Vt) Analog & devices

The gate voltage at which a transistor starts to conduct. Low-Vt cells are fast and leaky, and high-Vt cells are slow and low-leakage.

Transition fault Test (DFT)

A fault model for slow-to-rise or slow-to-fall nodes, used to catch delay defects with at-speed tests.

TSV Fab & packaging

Through-silicon via: a vertical connection through a die, used in 3D stacking and high-bandwidth memory (HBM).

U

Utilization Physical design

Cell area divided by available core area. It's a key floorplan target that leaves room for routing and optimization.

UVM Verification

Universal Verification Methodology: the standard SystemVerilog class library and methodology for building reusable testbenches (IEEE 1800.2).

V

Verification plan Verification

A document listing every feature to verify, how it will be checked, and the coverage goals that define done.

Virtual interface Verification

A handle that lets dynamic class objects in a testbench access a static SystemVerilog interface connected to the DUT.

W

Wafer Fab & packaging

A thin disc of crystalline silicon (typically 300 mm) on which many dies are fabricated at once.

X

X-propagation Verification

How unknown (x) values spread through logic in simulation. It can hide or create bugs, especially around resets.

Y

Yield Fab & packaging

The percentage of dies on a wafer that work. It's a key driver of chip cost.