Analog VLSI interview questions, with worked answers and solved numericals

A common-source stage with an ideal current-source load has gain A = g_mr_o, because the only resistance at the output is the device's own r_o. Any real load only adds parallel resistance and lowers it. So g_mr_o, the intrinsic gain, is the most one transistor can give.

With the square law, g_m = 2I_D/V_ov and r_o ≈ 1/(λI_D), so the current cancels and g_mr_o ≈ 2/(λV_ov). Short channels have a larger λ (channel-length modulation, DIBL), so intrinsic gain drops from around 100 in older nodes to around 10 in the most advanced ones.

Designers fight back with longer channels in analog devices, cascodes, which multiply output resistance by another g_mr_o, and more gain stages.

g_m/I_D is transconductance efficiency: how much g_m you get for each unit of current. It moves from about 25–30 S/A in weak inversion down to 5–10 S/A in strong inversion, and it maps one-to-one onto the inversion level.

• High g_m/I_D (15–25): low power and low V_ov, but large, slow devices. Good for low-noise input pairs.
• Low g_m/I_D (5–10): fast, small devices with good matching for current mirrors, at more current per g_m.

The flow is: pick g_m from the specification (for example GBW × 2πC_L), pick g_m/I_D from the trade-off, which gives I_D, then read the current density I_D/W from simulated lookup tables, which gives W. The method works in every inversion region, where square-law hand sizing breaks down.

A cascode device stacked on top of a transistor holds the lower device's drain at an almost constant voltage. Any change at the output appears across the cascode device, which has its own g_m working against it as local feedback. The result is R_out ≈ g_m2r_o2r_o1, roughly g_mr_o times higher than one device.

The cost:

• Headroom. Each extra device needs at least one V_ov across it, which matters at low supplies.
• Swing. Output swing shrinks by the same amount, which is why low-voltage designs move to folded cascodes or two stages.
• A bias voltage for the cascode gate, plus a pole at the cascode node, which is usually high enough not to matter.

• Common-mode rejection. Noise on the supply or substrate couples to both inputs equally and cancels in the difference.
• Double the swing. A differential output can swing twice the single-ended range on the same supply.
• Even-order cancellation. Symmetry cancels second-order distortion, improving linearity.
• A defined bias point set by the tail current rather than by an exact input DC level.

The costs are about twice the area and current for the same noise, and, for fully differential outputs, a common-mode feedback loop. Nearly every precision input stage accepts those costs.

With open-loop gain A and feedback factor β, the closed-loop gain is A/(1 + Aβ) ≈ 1/β when the loop gain Aβ is large. You give up a factor of (1 + Aβ) in gain, and in return many properties improve by that same factor:

• Gain accuracy: the gain is set by β, usually a capacitor or resistor ratio, instead of by transistor parameters that drift with process and temperature.
• Bandwidth extends by (1 + Aβ) for a single-pole amplifier; the gain–bandwidth product stays the same.
• Distortion falls, because the loop corrects the amplifier's non-linearity.
• Impedances move by (1 + Aβ) in the useful direction, depending on whether the loop senses or returns a voltage or a current.

The price is the risk of instability, because the loop adds phase shift, so every feedback amplifier needs a phase-margin check.

Flicker (1/f) noise comes from carriers being trapped and released by defects at the gate oxide interface. Its power spectral density rises as 1/f and scales roughly as 1/(WLC_ox), so it dominates at low frequency, below the noise corner where it meets the thermal floor.

• Bigger input devices: increasing WL lowers it directly, at the cost of capacitance and bandwidth.
• PMOS input devices often have lower 1/f noise in bulk CMOS processes.
• Circuit techniques: chopping or auto-zeroing move the noise out of the signal band.
• Keep the load devices quiet: their noise is input-referred through the ratio g_m,load/g_m,in, so give them a low g_m.

A single-stage OTA's GBW is g_m1/(2πC_L), so the required input g_m comes first:

gm1 = 2π · GBW · CL = 2π × 50 MHz × 2 pF ≈ 0.63 mS
pick gm/ID = 15 S/A  (moderate inversion: good noise and offset)
ID per side = 0.63 mS / 15 ≈ 42 µA   ->  tail ≈ 84 µA, call it 90 µA
W = ID / (ID/W from the lookup table at your chosen L)

Then check the rest: slew rate I_tail/C_L = 45 V/µs; mirror poles well above 50 MHz, so give the load mirror a lower g_m/I_D; gain g_m1(r_o2 ∥ r_o4) still meets the specification; headroom for the tail at the lowest input common-mode. Add margin, because GBW falls at the slow corner.

A common hand-design rule targets about 60° phase margin:

• GBW = g_m1/C_C sets the speed.
• The output pole p₂ ≈ g_m2/C_L should sit at least about 2.2× GBW.
• The right-half-plane zero g_m2/C_C should be about 10× GBW, or removed.

Combining the first two: g_m2/C_L ≥ 2.2 g_m1/C_C. With g_m2 ≈ 10 g_m1, that gives C_C ≥ 0.22 C_L.

A resistor R_Z in series with C_C moves the zero to 1/(C_C(1/g_m2 − R_Z)). R_Z = 1/g_m2 pushes it to infinity; a slightly larger R_Z moves it into the left half-plane, where it can cancel p₂ and buy back phase. Make R_Z from a triode MOSFET biased to track g_m2 over corners, then confirm the margin with a loop-gain simulation at every corner and load.

1. Sense the output common-mode: a resistor or capacitor divider between the two outputs, or a switched-capacitor sense in sampled circuits. Resistors load the output and lower gain; capacitors need refreshing; difference-pair sensing has limited range.
2. Compare it with the wanted level V_CM in a small error amplifier.
3. Correct by adjusting a current that sets the output common mode, usually part of the tail current or the load current sources.
4. Stabilise the loop. The CMFB loop has its own loop gain and poles, and it must be stable with at least the bandwidth of the signal path, or common-mode disturbances will appear during transients.

Check it with a common-mode step, a loop-gain simulation of the CM loop and large differential swings, where some sensing schemes stop being linear.

Pass device: size the PMOS so that at maximum load and the slowest corner it still conducts the current with only the dropout voltage across it. That's a very wide device with a large gate capacitance, which the error amplifier must drive.

Compensation depends on where the dominant pole sits:

• Large external capacitor: the output pole is dominant. Its frequency moves with load current, because the output resistance falls as load rises, and the capacitor's ESR adds a zero. The worst case is often light load.
• Capacitor-less (on-chip only): the output pole is at high frequency, so the error amplifier's output, at the pass device gate, is made dominant, often with Miller compensation across the pass device.

Then check stability over the full load range and corners, the load-step response, PSRR across frequency and the start-up behaviour.

Loop bandwidth decides which noise source wins:

• Inside the loop bandwidth, the output follows the reference (multiplied by N) and the charge pump and divider noise.
• Outside it, the output follows the VCO's own phase noise.

So the best bandwidth is roughly where the two contributions cross: wider if the VCO is noisy, as ring oscillators are; narrower if the reference is noisy or reference spurs must be filtered. A practical ceiling is about one-tenth of the reference frequency, because the loop is sampled once per reference cycle, and continuous-time analysis stops being valid near that point.

Then set the loop-filter zero and poles for about 60° of phase margin and check lock time, which shortens with wider bandwidth.

• Common-centroid placement (ABBA, or an ABBA/BAAB quad) so that linear gradients in oxide thickness or doping affect both devices equally.
• Same orientation and the same current direction for matched devices, because stress and implant angle depend on direction.
• Dummy fingers at the ends of each row, so every active finger has the same neighbours.
• Symmetric routing: equal wire lengths and the same metal layers for both sides, so parasitic resistance and capacitance match.
• Keep the pair away from hot or switching circuits and well edges, and use a guard ring.
• Use large area where offset matters, since random mismatch falls as 1/√(WL).

Then confirm with post-layout extraction and Monte Carlo on the extracted netlist.

Loop gain is T = Aβ. In a gain-of-10 configuration β = 0.1, so the loop crosses unity at about GBW/10, well below the op-amp's second pole. As a buffer, β = 1: the crossover moves up to the full GBW, closer to the non-dominant pole, and phase margin falls.

• Compensate for the worst case: if the part may be used as a buffer, design for β = 1.
• Or document it as stable only above a minimum gain (“decompensated” op-amps trade this for higher speed).
• Check capacitive loading too, since a load capacitor lowers the output pole and makes buffers ring even more.

The output device's V_DS follows the supply while the reference device's stays fixed, so channel-length modulation changes the current. A 10% change for a 0.2 V step means r_o = ΔV/ΔI = 0.2 V/(0.1·I) = 2 V/I, an Early voltage of only about 2 V, which points to a very short channel.

• Use a longer L for the mirror devices, which raises r_o and also improves matching.
• Add a cascode (or a wide-swing cascode if headroom is tight) to hold the mirror's V_DS constant.
• Make the reference V_DS equal to the output V_DS at the operating point, for example with a matching dummy branch.

Also check that the reference current itself doesn't come from a resistor to the supply, which would move it directly.

Unchanged DC gain means the operating point is fine; the loss is in capacitance or resistance on high-impedance nodes.

• Wiring capacitance on the output or on the internal node that sets the non-dominant pole. A long route to the load adds femtofarads that matter at high impedance.
• Miller-multiplied coupling between input and output wires of a gain stage.
• Series resistance in the compensation or load path, or gate resistance in wide devices with too few fingers.
• Well and junction capacitance that the schematic models missed.

Compare node capacitances between schematic and extracted netlists, back-annotate the worst ones into the schematic and rerun the AC analysis. Fix it by shortening and thinning critical routes, adding fingers, or moving a sensitive wire away from large nets.

A frequency-independent error points to a static cause, usually the op-amp's finite DC gain. With feedback factor β = C_f/(C_s + C_f + C_p), the closed-loop gain error is about 1/(Aβ).

Cs = 4 pF, Cf = 1 pF, Cp = 0.5 pF  ->  β = 1/5.5 ≈ 0.18
error 0.5%  ->  Aβ ≈ 200  ->  A ≈ 1100 (61 dB)

• Raise the op-amp's DC gain (cascoding, gain boosting or another stage).
• Reduce parasitic capacitance C_p at the op-amp input, which lowers β.
• Check capacitor ratio accuracy too: a systematic ratio error from layout also gives a fixed gain error.

A settling error, by contrast, gets worse as the clock speeds up.

The first-order design cancels the linear part of V_BE's temperature dependence with a PTAT term. But V_BE also has a curvature term (roughly T·ln T), which a linear PTAT term can't cancel. The output therefore has a parabolic shape, highest near the temperature where the slopes cancel, falling at both ends. A few millivolts over the industrial range is typical for an uncorrected bandgap.

• Make sure the peak sits in the middle of the range; if not, the PTAT gain (the resistor ratio) is off, which trimming corrects.
• If the bow itself is too large, add curvature correction: a small non-linear current that cancels the T·ln T term.
• Check that op-amp offset and resistor temperature coefficients aren't adding to it.

Errors that grow with input frequency come from the sampling instant or the sampling switch:

• Clock jitter: the error is the signal slope times the timing error, so SNR_jitter = −20 log(2πf_inσ_t) falls by 6 dB for every doubling of input frequency.
• Sampling-switch non-linearity: the switch's on-resistance varies with the signal, so the tracking error is signal-dependent. Bootstrapped switches keep V_GS constant to fix this; this shows mainly as distortion (SFDR) rather than noise.
• Input bandwidth: the front-end's settling or bandwidth may be marginal near Nyquist.

Separate them by looking at the FFT: a raised noise floor points to jitter, harmonics point to the switch or front-end. Then measure with a cleaner clock source.