How many rounds does a DFT interview usually have?

Usually two or three: a fundamentals round on fault models, scan, ATPG and coverage with a numerical or two, an architecture round on at-speed test, compression, BIST, MBIST and JTAG, and for experienced candidates a debugging or silicon bring-up round.

Will I get numerical questions in a DFT interview?

Very likely. Common ones are scan test time with and without compression, test coverage from fault classes, defect level from yield and coverage, LFSR sequences, March test time and JTAG chain lengths.

Do I need hands-on experience with a specific DFT tool?

No. Fault-class names and commands differ between vendors, so interviewers test concepts: why scan works, how coverage is computed, why X-values break compression, LOC vs LOS. Mention the tools you actually used and focus on what you did with them.

Is DFT a good career track for freshers?

Yes. Every chip that ships needs manufacturing test, and DFT roles exist at design houses, EDA companies and service companies. It also sits between design, physical design and test engineering, which builds broad skills.

How should a fresher prepare for DFT questions?

Start with fault models, scan design, shift and capture, ATPG and fault classes. Then learn at-speed LOC and LOS, compression basics, March algorithms and the JTAG TAP. Practise the numericals until they are automatic, and prepare one or two project stories with real numbers.

DFT Interview Questions (2026): 90+ with Answers

Q: What is the difference between test coverage and fault coverage?

Both count detected faults (plus partial credit for possibly detected ones). Fault coverage divides by all faults; test coverage divides by testable faults only, removing faults proven undetectable. Test coverage is therefore always greater than or equal to fault coverage.

DFT interviews ask a different question from design interviews: not "does the chip work?", but "can we prove every manufactured chip works, quickly and cheaply?" That's why they mix concepts with numbers. You'll be asked to compute a test time, explain why coverage is stuck, or say what to check when the scan chain fails on every die.

This page is built around that. Start with the formula sheet and the calculator, browse 50 questions across ten topics, then work through the worked answers, numericals and the ATPG report walkthrough. Try each one aloud before opening the answer.

HOW IT'S STRUCTURED

What a DFT interview actually looks like

ROUND 1

Fundamentals & numericals

Fault models, scan flops, shift and capture, ATPG, test vs fault coverage, and usually a calculation: test time, coverage from fault classes, or collapsed fault counts.

ROUND 2

Architecture

LOC vs LOS and the OCC, how compression works and why X-values hurt it, LBIST and MBIST, the JTAG TAP, IJTAG and core wrappers. Expect to draw at least one block diagram.

ROUND 3

Debugging & silicon

Common from 2–3 years of experience: coverage stuck below target, chains failing on first silicon, at-speed fails, pattern simulation mismatches, test time over budget.

HOW TO ANSWER

Six habits that make DFT answers land

Explain why the structure exists

"Scan turns a sequential ATPG problem into a combinational one" says more than any definition. Interviewers listen for the why behind scan, OCCs, lock-up latches and wrappers.

Draw it

A mux-D scan flop, the shift/capture waveform, LOC vs LOS, PRPG → chains → MISR, the TAP state machine. A quick sketch earns full marks fast.

Say which coverage you mean

Test coverage and fault coverage have different denominators, and collapsed and uncollapsed counts differ. Name the definition before you quote a number.

Think in test cost

Test time, tester memory, multi-site, overkill vs escapes, DPPM. Tying a DFT choice to cost and quality signals production maturity.

Treat X as the enemy

Uninitialised memories, black boxes, non-scan flops and bus contention create X. Mention how they hurt coverage, compression and LBIST, and how you'd bound them.

Classify before debugging

All dies fail or some? Chain or logic? Stuck-at or at-speed only? Classify, verify the setup, isolate, find the root cause, then re-verify across modes and corners.

FORMULA SHEET

Every DFT number you'll be asked to work out

P = patterns, L = longest chain, C = capture cycles per pattern, PD credit is usually 50%.

SCAN TEST CYCLES≈ (P + 1) × L + P × CLoad and unload overlap; the "+1" is the final unload.

TEST TIMEcycles / f_shiftShift dominates; capture cycles are few.

CHAIN LENGTHL = scan flops / number of chains (balanced)

DATA VOLUMEuncompressed ≈ 2 × flops × P bits; compressed ≈ (in + out channels) × L × P

TEST COVERAGE(DT + 0.5·PD) / (all faults − undetectable)

FAULT COVERAGE(DT + 0.5·PD) / all faultsAlways ≤ test coverage.

DEFECT LEVELDL = 1 − Y^(1−T) (Williams–Brown); DPPM = DL × 10⁶

YIELDY = e^−A·D₀ (Poisson; A = die area, D₀ = defect density)

LFSR / MISRmax period 2ⁿ − 1; aliasing ≈ 2⁻ⁿ

RANDOM DETECTIONN ≥ ln(1 − confidence) / ln(1 − p)

STUCK-AT FAULTS2 per pin; an n-input simple gate collapses to n + 2

MARCH TESTSMATS+ = 5N · March C− = 10N · March B = 17N (N = words)

TRY IT

Scan test-time calculator

Set internal chains equal to channels for plain scan; raise it to see what compression does.

SCAN FLOPS

SCAN CHANNELS (IN)

INTERNAL CHAINS

PATTERNS

CAPTURE CYCLES / PATTERN

SHIFT FREQUENCY (MHz)

CHAIN LENGTH–

TEST CYCLES–

TEST TIME–

COMPRESSION RATIO–

FAULT MODEL	PATTERNS	SPEED	TARGETS	TYPICAL USE
Stuck-at	1 (load, capture)	Slow	Node fixed at 0 or 1	Baseline production test
Transition	2 (launch, capture)	At-speed	Slow-to-rise / slow-to-fall	Delay defects, LOC/LOS
Path delay	2	At-speed	Specific critical paths	Speed paths, binning
Small delay	2, timing-aware	At-speed	Longest path through each fault	Quality at advanced nodes
Bridging	1+	Slow	Shorts between layout neighbours	Defect-oriented test
Cell-aware	1 or 2	Slow or at-speed	Defects inside standard cells	DPPM reduction, automotive
IDDQ	A few vectors	Measured	Leakage defects	Bridges, oxide defects

BROWSE BY TOPIC

50 DFT interview questions across 10 topics

A sample of what interviewers draw from most. The full 575-question ebook covers each topic in much more depth, with every question answered.

Test Fundamentals

Why manufacturing test exists and what it measures.

What is the difference between verification and manufacturing test?
What is the difference between a defect, a fault and a failure?
Define controllability and observability with an example.
What are overkill and test escapes, and which costs more?
What does DPPM measure, and why do automotive customers care so much about it?

Fault Models

How real defects are abstracted for ATPG.

Why is the stuck-at model still used when most real defects aren't stuck-at?
How many collapsed stuck-at faults does a 3-input NAND have?
What is the difference between fault equivalence and fault dominance?
What is a transition fault, and why does it need two patterns?
What is cell-aware test, and what does it catch that stuck-at misses?

Scan Design & Test Rules

Making every flop controllable and observable.

Draw a mux-D scan flop. What does it cost in area and timing?
Walk through one scan pattern from load to unload.
Why must asynchronous resets be controllable in test mode?
What is the difference between scan enable and test mode?
What are common X-sources, and how do you bound them?

ATPG & Coverage

Generating patterns and proving how good they are.

Explain fault excitation and propagation (sensitisation) for a simple gate.
What is the difference between test coverage and fault coverage?
What do DT, PD, UD, AU and ND mean in an ATPG report?
Why does a redundant fault count as undetectable, and what does it say about the logic?
What are ATPG constraints, and how can over-constraining lower coverage?

At-Speed Test: LOC, LOS & OCC

Catching delay defects with a slow tester.

Why can't you run at-speed test using the tester clock directly?
Compare launch-off-capture and launch-off-shift on coverage, SE timing and overtesting.
What does an on-chip clock controller do, and why must it be glitch-free?
Why must at-speed ATPG honour SDC false paths and multicycle paths?
How do you handle transition faults on paths between two clock domains?

Test Compression

Cutting test time and tester memory by 10–100×.

Why does compression work? Explain care bits.
What do the decompressor and compactor each do?
Why do X-values hurt a compactor, and how does X-masking help?
Pattern count went up after enabling compression. Is that a problem?
What limits how high you can push the compression ratio?

Logic BIST & Memory BIST

Letting the chip test itself.

Draw a STUMPS LBIST architecture. Why must the design be X-free?
What are random-pattern-resistant faults, and how do test points help?
Write March C− and say which faults each element targets.
Why does March C− use both ascending and descending address order?
How does memory repair work, from BIRA to eFuse to power-up?

JTAG, IJTAG & Core Wrappers

Standard ways to reach test logic.

Name the JTAG pins and the mandatory instructions.
What TMS sequence takes the TAP from Run-Test/Idle to Shift-DR?
Why does TDO change on the falling edge of TCK?
What is a SIB in IEEE 1687, and what are ICL and PDL used for?
What is the difference between INTEST and EXTEST in an IEEE 1500 wrapper?

Test Timing, Power & Physical Scan

Where DFT meets STA and physical design.

Why are scan shift paths prone to hold violations, and how are they fixed?
What is a lock-up latch, and where is it inserted?
Why is scan chain reordering done after placement?
Why is power during test higher than in functional mode?
Which modes need test-mode STA, and what constraints does each use?

Diagnosis, Production & Silicon Debug

What happens after the patterns reach the tester.

How does the 0011 chain test pattern reveal the type of a chain defect?
What is volume diagnosis, and what does it reveal that single-die analysis can't?
Why do patterns pass in zero-delay simulation but fail with SDF?
The chain test fails on every die. Where do you start?
Test time is 40% over budget. What options do you propose?

WORKED ANSWERS

18 DFT questions, answered the way interviewers expect

Try each one out loud first, then open it. Every answer shows what a strong reply covers, what the interviewer is really listening for, and the mistake that costs candidates the most.

01What is DFT, and how is manufacturing test different from verification?Foundational

Verification asks whether the design is correct: does the RTL do what the spec says? It's done once, before tape-out. Manufacturing test asks whether each fabricated chip matches the design: did a particle, short or open break this particular die? It runs on every chip, on a tester, in seconds.

Design for Testability adds structures that make that test possible and cheap: scan chains so every flop can be set and read, ATPG patterns, compression to cut tester time, BIST for memories and logic, and JTAG for access.

The goal is high defect coverage at low test cost: few escapes (bad chips shipped, measured in DPPM) and little overkill (good chips rejected).

Interviewers listen for"Correct design" vs "correctly manufactured chip", and the cost/quality framing.

Common mistakeDescribing DFT as functional verification with test patterns.

02What is the stuck-at fault model, and why is it still used?Foundational

A stuck-at fault assumes one node is permanently tied to 0 (SA0) or 1 (SA1). Every pin has two such faults. To detect one, ATPG must excite it (drive the node to the opposite value) and propagate the difference to an observable point by setting side inputs to non-controlling values.

Real defects are shorts, opens and resistive vias, not perfect stuck nodes. Stuck-at is still the baseline because it's simple, scales to billions of faults, and patterns that detect all stuck-at faults also catch a large share of real defects. Transition, cell-aware and bridging models are added on top for what it misses.

Fault lists are collapsed: an n-input AND/NAND/OR/NOR gate has 2(n+1) faults, collapsing to n + 2.

Interviewers listen forExcite + propagate, and a reason the model survives.

Common mistakeClaiming stuck-at coverage alone is enough for advanced nodes.

03How does scan design work? Walk through one scan pattern.Foundational

Each flop is replaced by a mux-D scan flop: a 2:1 mux in front of D selects functional data when scan enable (SE) = 0 and the scan input (SI) when SE = 1. Flops are stitched SO → SI into chains between scan-in and scan-out pins.

Load: SE = 1, shift L clock cycles to put a value in every flop (and unload the previous response at the same time).
Apply primary inputs.
Capture: SE = 0, pulse the functional clock once (twice for at-speed). Every flop captures its logic cone's response.
Unload: SE = 1, shift the response out while loading the next pattern.

This makes every flop a pseudo-input and pseudo-output, so ATPG only has to solve combinational logic between flops.

Interviewers listen for"Sequential problem becomes combinational", and load/unload overlap.

Common mistakeForgetting the cost: the mux adds delay to the functional D path and area to every flop.

04What are controllability and observability? How do test points help?Foundational

Controllability is how easily a node can be set to 0 or 1 from the inputs. Observability is how easily its value can be seen at an output. A node deep in a 16-input AND tree is hard to set to 1 (all inputs must be 1); a node feeding only a long chain of logic is hard to observe.

Scan makes every flop fully controllable and observable. Inside combinational logic, test points fix what's left: a control point (an OR/AND gate with a test-only input) forces a hard node, and an observe point (a scan flop tapping the node) captures it directly.

Test points matter most for LBIST, where random patterns rarely hit hard-to-control nodes, but they also cut deterministic pattern counts.

Interviewers listen forAn example of each, and the matching type of test point.

Common mistakeIgnoring the cost: test points add area and can sit on timing-critical paths.

05What's the difference between test coverage and fault coverage?Foundational

Fault coverage = (DT + 0.5·PD) / all faults
Test coverage  = (DT + 0.5·PD) / (all faults − UD)

Both count detected faults (DT) plus partial credit for possibly detected faults (PD, where the faulty value is X at the observation point). Test coverage removes faults proven undetectable (unused, tied, blocked, redundant) from the denominator, because no pattern could ever detect them. So test coverage is always ≥ fault coverage.

Most teams sign off on test coverage, but you should always say which one, and whether the fault list is collapsed or uncollapsed, because the numbers differ.

Interviewers listen forThe denominators, and why UD faults are excluded.

Common mistakeUsing the terms interchangeably, or quoting a number without saying which.

06What is a transition fault, and why do we need at-speed test?Foundational

A transition fault models a node that is slow to rise or slow to fall: the logic value is right, but it arrives too late. Resistive vias, weak transistors and small bridges cause this, and stuck-at patterns applied at slow tester speed can't see it.

Detection needs two patterns: the first sets the node to the initial value, the second launches the transition, and the response is captured exactly one functional clock period later. If the transition didn't arrive in time, the wrong value is captured.

Because the tester's own clock is slow and noisy, the launch and capture pulses are usually generated on-chip by an OCC from the PLL.

Interviewers listen forTwo patterns, and capture at functional speed.

Common mistakeSaying transition test is "stuck-at at a faster clock".

07Compare LOC and LOS. What does the OCC do?Applied

Both launch a transition and capture it one functional period later. They differ in how the launch happens:

Launch-off-shift (LOS): the last shift cycle launches the transition, then SE drops and the capture pulse follows at-speed. Launch values come straight from shifting, so coverage is higher with fewer patterns. But SE must switch within one functional period (an at-speed SE network), and shift-based launches can exercise functionally impossible transitions (overtesting).
Launch-off-capture (LOC): SE drops during slow shift, then two at-speed functional pulses launch and capture. No at-speed SE, and only functionally reachable transitions; coverage is lower and patterns more.

The on-chip clock controller passes the slow tester shift clock during shift, then gates exactly two (or more) PLL pulses for capture, glitch-free and synchronised to SE. Most designs use LOC with OCCs.

Interviewers listen forThree axes: coverage, SE timing, overtesting.

Common mistakeSaying LOS is always better because it has higher coverage.

08How does scan compression work, and why do X-values matter?Applied

A typical ATPG pattern needs only a few percent of its scan bits to be specific values (care bits); the rest are don't-care. Compression exploits that:

A decompressor (often a ring generator or XOR network) expands a few tester channels into hundreds of short internal chains. ATPG solves for channel data that produces the needed care bits.
A compactor (XOR tree) merges hundreds of chain outputs into a few output channels.

Short chains mean far fewer shift cycles per pattern, so test time and data volume drop 10–100×, even if pattern count rises.

X-values are the problem: one unknown bit entering an XOR compactor corrupts every output it combines with, hiding real fault effects. Designs fix X at the source (bound memories, initialise flops) and use X-masking to block X chains per pattern.

Interviewers listen forCare bits as the reason it works, and X as the reason it fails.

Common mistakeThinking compression reduces the number of patterns.

09What are X-sources, and how do you deal with them?Applied

An X-source is anything whose value ATPG can't predict in test mode:

Memories and black boxes without models
Non-scan flops and latches that aren't initialised
Analog blocks, PLLs and I/O pads with unknown outputs
Bus contention or floating tri-states
Multicycle or false paths captured at speed, and asynchronous clock crossings

Fixes: bound them with test-mode logic that forces a known value (an AND/OR gate driven by test mode), wrap memories with scannable collars or use memory models, make or initialise the flops, add X-masking in the compactor, and mark at-speed paths that aren't valid so their captures are masked.

Interviewers listen forA list of real sources, and that X hurts coverage (PD/AU faults), compression and LBIST.

Common mistakeTreating X as only a simulation nuisance rather than a coverage and quality problem.

10Explain logic BIST. Why must the design be X-free?Applied

In the common STUMPS architecture, a PRPG (an LFSR plus a phase shifter) feeds pseudo-random data into the scan chains, the chains capture, and a MISR compacts all chain outputs into one signature. A controller sequences shift and capture and compares the final signature with the golden value, reporting pass/fail through JTAG or IJTAG.

There's no tester to mask anything, so a single X anywhere corrupts the whole signature. The circuit under test must be fully X-bounded.

Random patterns also struggle with random-pattern-resistant faults: an output of a 10-input AND needs all inputs at 1, probability 1/1,024 per pattern. Test points raise those probabilities. LBIST is popular for in-system test in automotive designs (ISO 26262).

Interviewers listen forThe PRPG → chains → MISR picture, X-bounding and test points.

Common mistakeForgetting MISR aliasing (≈ 2⁻ⁿ), which is why MISRs are 32 bits or more.

11How is memory tested, and how does repair work?Applied

Embedded memories are too dense and too numerous to test with scan, so each gets MBIST: a controller and a collar that run March algorithms at speed. March C− (10N):

⇕(w0); ⇑(r0,w1); ⇑(r1,w0); ⇓(r0,w1); ⇓(r1,w0); ⇕(r0)

It catches stuck-at, transition, address-decoder and many coupling faults; running both address directions is what catches coupling between cells.

Repair: memories have spare rows or columns. BIRA (built-in redundancy analysis) decides which spares cover the failing cells; the result is stored in eFuses. At every power-up, the repair data is loaded into the memories (BISR) before use.

Interviewers listen forWriting March C− from memory, and the eFuse-to-power-up chain.

Common mistakeForgetting that repair must be re-tested after it's applied.

12Explain JTAG. How do IJTAG and IEEE 1500 build on it?Applied

IEEE 1149.1 (JTAG) defines a test access port with TCK, TMS, TDI, TDO and optional TRST*, a 16-state TAP controller, an instruction register and data registers. The boundary-scan register sits on every I/O so board interconnects can be tested. Mandatory instructions: BYPASS (a 1-bit register, opcode all 1s), SAMPLE/PRELOAD and EXTEST. Holding TMS = 1 for five TCK cycles resets the TAP from any state.

IEEE 1687 (IJTAG) extends access to hundreds of on-chip instruments (MBIST controllers, sensors, PLL controls) through a reconfigurable network of SIBs and test data registers, described in ICL and driven by PDL that tools retarget to the chip pins.

IEEE 1500 wraps embedded cores with a wrapper boundary register, so each core can be tested in isolation (INTEST) and its surroundings tested from outside (EXTEST).

Interviewers listen forPins, TAP reset, mandatory instructions, and which standard solves which access problem.

Common mistakeThinking JTAG is fast enough for internal logic test; it's for access and board test.

13Stuck-at coverage is stuck at 94% and the target is 99%. What do you do?Scenario / debug

Break the gap down by fault class (AU, ND, PD) and by hierarchy. One block or one class usually holds most of it.
AU faults (untestable under current setup) are usually the biggest lever: look for X-sources around memories and black boxes, non-scan flops, tied test-mode pins, clock domains not pulsed, and over-constrained ATPG settings.
PD faults: bound the X-sources that make the faulty value unknown.
ND faults: separate not-controlled from not-observed; add control or observe points, raise ATPG effort for aborted faults.
Check DFT DRC warnings: many coverage losses are flagged there first.
Re-run after each fix and track the gain per change.

Interviewers listen forA prioritised, data-driven process.

Common mistakeJumping to "add test points" or "raise effort" before finding where the faults are.

14The scan chain test fails on every die in first silicon. Where do you start?Scenario / debug

Every die failing means a systematic problem, not random defects. Suspect the setup and the design first:

Test-mode entry: the JTAG/IJTAG sequence or pin straps that put the chip in scan mode.
Pins: scan-in/out pad direction, pin mapping in the test program, the scan-enable pin.
Clocks: is the OCC or PLL correctly bypassed for slow shift? Is the shift clock reaching the chains?
Reset and watchdogs that disturb the chains during shift.
Shift timing: lower the shift frequency and sweep voltage (shmoo). If it passes slowly, suspect a shift setup problem; if it fails at any speed, suspect hold or connectivity.

Then compare the tester log with a simulation of the exact tester pattern.

Interviewers listen for"All dies fail = setup or design; some dies fail = defects."

Common mistakeStarting with defect diagnosis and failure analysis on a systematic failure.

15Only one chain out of 64 fails on most dies. What's likely?Scenario / debug

A problem specific to that chain's implementation, not the overall setup:

A shift hold violation between two cells on different clock branches with large skew, often a missing lock-up latch where the chain crosses domains or clock edges.
Chain order changed by reordering but not written back, so ATPG expects the wrong order.
A scan-enable timing problem in one region, or a pad/channel issue on that scan pin.

Check test-mode STA for shift on that chain, simulate shift with SDF, and run chain diagnosis on the fail data to locate the failing cell. The 0011 chain-test pattern shows whether it's stuck, slow-to-rise/fall, or a hold-type "jump".

Interviewers listen forShift hold and lock-up latches as the prime suspects.

Common mistakeSaying hold doesn't matter in scan because shift is slow. Hold doesn't depend on frequency.

16At-speed patterns fail on 30% of dies, but stuck-at passes. What do you check?Scenario / debug

A fail rate that high is rarely real delay defects. Check the test before blaming the silicon:

Exceptions: did at-speed ATPG import the SDC false and multicycle paths? Without them, patterns test paths that are never required to meet one cycle.
IR drop during at-speed capture: many flops switching at once slows paths that are fine functionally. Look for failures clustered in high-activity regions; use low-power capture or power-aware ATPG.
OCC configuration: correct pulse count and launch-to-capture interval for each domain.
Timing margin: do failing paths have small slack at the test corner? Shmoo frequency and voltage.
Look for common failing flops or paths across dies; that points to a systematic cause.

Interviewers listen forOverkill awareness: exceptions and test power before defects.

Common mistakeConcluding the silicon is slow and lowering the test frequency without root cause.

17ATPG patterns pass zero-delay simulation but fail a few cells with SDF. Why?Scenario / debug

Zero-delay simulation checks logic only; SDF simulation adds real timing, so the failures are timing problems in test mode:

Capture-only failures usually mean hold or race issues in capture: clock skew between domains pulsed together, or a path that isn't timed in the test-mode SDC.
Shift failures point to shift hold on SO → SI connections or a missing lock-up latch.
At-speed patterns may capture through a multicycle or false path that ATPG should have masked.

Check test-mode STA for the failing endpoints, confirm the SDF corner matches, and check whether those captures should be masked. Fix the design or the constraints, not the expected values.

Interviewers listen forSeparating shift from capture failures, and linking to test-mode STA.

Common mistakeMasking failing cells without understanding why they fail.

18Test time is 40% over budget. What options do you propose?Scenario / debug

Start with where the time goes (shift cycles, pattern count, MBIST, other tests), then rank options by gain and cost:

Raise the compression ratio (more, shorter internal chains). Watch for pattern count growth from encoding limits.
Raise shift frequency if shift timing and test power allow.
Cut pattern count: test points for hard faults, better ATPG settings, removing redundant pattern sets.
Test cores in parallel or use a streaming scan network, within the power budget.
Multi-site testing on the tester to raise throughput per die.
Run MBIST concurrently with other tests where power allows.

Then re-check coverage and power for every change.

Interviewers listen forMeasuring first, then trade-offs for each option.

Common mistakeDropping pattern sets and losing coverage just to meet the time.

SOLVED NUMERICALS

8 DFT numericals, solved step by step

DFT interviews regularly include quick calculations. Work each one on paper first, then tap to check.

N1 · SCAN TEST TIMEBEGINNER240,000 scan flops in 24 balanced chains, 2,500 patterns with 1 capture cycle each, shift at 25 MHz. Estimate the test time.Show solution ↓

L      = 240,000 / 24 = 10,000
Cycles ≈ (2,500 + 1) × 10,000 + 2,500 × 1
       = 25,012,500
Time   = 25,012,500 × 40 ns ≈ 1.0 s

Note: the "+1" is the final unload; every other unload overlaps the next load.

N2 · WITH COMPRESSIONINTERMEDIATESame design with 1,200 internal chains. Pattern count rises to 5,000. New test time and reduction?Show solution ↓

L      = 240,000 / 1,200 = 200
Cycles ≈ 5,001 × 200 + 5,000 = 1,005,200
Time   = 1,005,200 × 40 ns ≈ 40.2 ms
Gain   ≈ 1.0 s / 40.2 ms ≈ 25×

Note: twice the patterns, 25× less time. Compression cuts cycles per pattern, not patterns.

N3 · COVERAGEBEGINNER80,000 faults: 2,000 undetectable, 75,600 detected, 600 possibly detected (50% credit), the rest undetected. Test and fault coverage?Show solution ↓

Credited = 75,600 + 0.5 × 600 = 75,900
Test cov  = 75,900 / (80,000 − 2,000) = 97.31%
Fault cov = 75,900 / 80,000          = 94.88%

Note: test coverage is higher because undetectable faults leave the denominator.

N4 · DEFECT LEVELINTERMEDIATEYield is 80%. What's the defect level at 99% coverage, and at 99.9%?Show solution ↓

DL = 1 − Y^(1−T)
T = 0.99 : 1 − 0.8^0.01  ≈ 0.00223 → ≈ 2,230 DPPM
T = 0.999: 1 − 0.8^0.001 ≈ 0.00022 → ≈   223 DPPM

Note: 0.9% more coverage cuts escapes about 10×. That's the business case for the last fraction of a percent.

N5 · LFSR SEQUENCEINTERMEDIATEA 3-bit LFSR shifts Q1 → Q2 → Q3 with Q1⁺ = Q1 ⊕ Q3. Starting from 001, list the states. Is it maximal length?Show solution ↓

Q1+ = Q1 ⊕ Q3,  Q2+ = Q1,  Q3+ = Q2
001 → 100 → 110 → 111 → 011 → 101 → 010 → 001

Note: 7 distinct non-zero states = 2³ − 1, so yes. All-zero is excluded: an XOR-feedback LFSR would stay at 000 forever.

N6 · MEMORY TEST TIMEINTERMEDIATEA 256K-word memory is tested with March C− at 500 MHz, one operation per cycle. How long? And with MATS+?Show solution ↓

N = 262,144 words
March C− : 10N = 2,621,440 × 2 ns ≈ 5.24 ms
MATS+    :  5N = 1,310,720 × 2 ns ≈ 2.62 ms

Note: complexity counts word operations, not bits; word width doesn't change it.

N7 · JTAG CHAININTERMEDIATEThree devices on a board chain have IR lengths 5, 4 and 6. Device 2 runs EXTEST with a 250-cell boundary register; the others are in BYPASS. IR and DR lengths?Show solution ↓

IR length = 5 + 4 + 6 = 15 bits
DR length = 1 + 250 + 1 = 252 bits

Note: each BYPASS register is 1 bit. That's exactly why BYPASS exists: to keep the chain short when you only talk to one device.

N8 · RANDOM-RESISTANT FAULTADVANCEDThe output SA0 of an 8-input AND needs all inputs at 1. With random patterns, how many are needed for 99% detection probability?Show solution ↓

p = 2^−8 = 1/256 per pattern
N ≥ ln(0.01) / ln(1 − 1/256)
  ≈ −4.605 / −0.00391 ≈ 1,177 patterns

Note: at 16 inputs, p = 1/65,536 and N grows to about 300,000. That's why LBIST needs control test points.

READ AN ATPG REPORT

Walk through a transition-fault coverage report

"Here's our ATPG report. What would you do next?" is a standard question. This one is for transition faults, where coverage is lower and the reasons are different from stuck-at. Generic, tool-neutral format.

ATPG Statistics   Fault model: transition (LOC)   Mode: compression
Design: gpu_cluster_top   Collapsed: no   PD credit: 50%

  Fault class                               # faults
  -----------------------------------------------------
  DT  detected                             2,150,400   (1)
  PD  possibly detected                        4,800   (2)
  UD  undetectable                            96,000   (3)
        UU unused        21,600
        UT tied          38,400
        UB blocked       24,000
        UR redundant     12,000
  AU  ATPG untestable                         98,400   (4)
  ND  not detected                            50,400   (5)
        NC not controlled  18,000
        NO not observed    32,400
  -----------------------------------------------------
  Total faults                             2,400,000

  Test coverage  = (DT + 0.5*PD)/(Total - UD)   93.44 %  (6)
  Fault coverage = (DT + 0.5*PD)/Total          89.70 %  (7)

  Patterns: 9,850   Chains: 960 (max 250)   Channels: 8/8
  Capture cycles: 2   Shift: 50 MHz   Test time: 49.6 ms  (8)

Detected faults, including those credited by the chain test.
Possibly detected: the faulty value is X when observed. Fix the X-sources.
Proven undetectable. Removed from the test-coverage denominator.
The biggest lever: 98,400 faults, 4.3% of testable faults. Untestable only under the current setup.
Not observed (32,400) outweighs not controlled (18,000): observe points will help more than control points.
(2,150,400 + 2,400) / 2,304,000 = 93.44%.
2,152,800 / 2,400,000 = 89.70%.
(9,851 × 250) + (9,850 × 2) ≈ 2.48 M cycles × 20 ns ≈ 49.6 ms.

Where would you look first to raise coverage?

The AU faults: 98,400 of them, more than ND and PD combined. For transition faults, AU usually comes from the test setup: clock domains whose OCCs can't launch and capture together, inter-domain paths that aren't allowed, faults on false or multicycle paths excluded by the SDC, memory and black-box X-sources, and non-scan flops. Report AU by hierarchy and by reason, then fix the biggest bucket.

Why is transition coverage usually lower than stuck-at?

Each transition fault needs two patterns with a timed launch and capture, so it's harder to control. Paths that can't be exercised at speed (exceptions, slow I/O, cross-domain paths) are excluded, and OCC and clocking constraints remove more. Transition coverage in the low-to-mid 90s is common where stuck-at reaches 98–99%+, but targets are set per project.

What would you do about the 4,800 PD faults?

PD means the good value is known but the faulty value is X at the observation point. Find the X-sources reaching those flops (uninitialised memories, black boxes, non-scan cells) and bound them. Fixing PD also helps compression, since X-values force masking.

Is test coverage or fault coverage the number to report?

Usually test coverage, but say which, and whether the fault list is collapsed. Here the 3.7-point gap between them is the 96,000 undetectable faults. If UU (unused) is large, it's worth telling the design team: it often means dangling logic left by synthesis. The ebook walks through a full stuck-at report with eight callouts.

RAPID-FIRE ROUND

20 quick questions, one-line answers

Screening rounds often open with fast checks like these. Aim to answer each in under ten seconds, then tap to check.

How many stuck-at faults per pin?

Two: SA0 and SA1.

Collapsed faults on an n-input NAND?

n + 2.

Scan enable value during shift?

SE = 1 (shift); SE = 0 for capture.

What sets the shift cycles per pattern?

The longest scan chain.

Test coverage or fault coverage: which is higher?

Test coverage. Undetectable faults leave its denominator.

What does PD mean?

Possibly detected: the faulty value is X at the observation point.

How many patterns does a transition fault need?

Two: one to initialise, one to launch.

Which needs an at-speed scan enable, LOC or LOS?

LOS.

What does an OCC generate?

Slow shift clocks and at-speed launch/capture pulses from the PLL.

What makes compression possible?

Care bits are a small fraction of each pattern.

Max period of an n-bit LFSR?

2ⁿ − 1, with a primitive polynomial.

MISR aliasing probability?

About 2⁻ⁿ for an n-bit MISR.

Complexity of March C−?

10N.

Where is memory repair data stored?

In eFuses, loaded into the memories at power-up.

Name the JTAG pins.

TCK, TMS, TDI, TDO, and optional TRST*.

How do you reset the TAP from any state?

Hold TMS = 1 for five TCK cycles.

BYPASS register length?

1 bit; opcode all 1s.

What is a SIB?

A segment insertion bit: it opens or closes a segment of an IJTAG network.

What does a lock-up latch fix?

Shift hold violations where a chain crosses clock domains or skewed branches.

What file passes scan chains to place-and-route?

SCANDEF.

AT A GLANCE

DFT structures: what each one solves and what it costs

A one-screen revision table for the night before the interview.

STRUCTURE	WHAT IT SOLVES	WHAT IT COSTS
Scan chains	Controllability and observability of every flop	Mux delay on D, area, routing, shift hold
Compression	Test time and tester memory (10–100×)	More patterns, X-sensitivity, decompressor area
OCC	Accurate at-speed launch and capture	Clock-path logic, careful glitch-free design
Test points	Hard-to-control and hard-to-observe nodes	Area, possible timing impact
Lock-up latch	Shift hold across domains or skewed branches	Small area; must be placed correctly
Logic BIST	In-system and in-field test without a tester	X-bounding, test points, lower coverage than ATPG
MBIST + repair	Dense memories, yield recovery with spares	Collars, controllers, eFuses, test time
JTAG (1149.1)	Board interconnect test, standard access	Boundary cells on every I/O; slow
IJTAG / 1500	Access to many instruments; core-level test	Network and wrapper area, retargeting setup

Full 575-question DFT ebook (with answers) →STA interview questions →Physical design interview questions →Take the timed quiz →Look up any term in the glossary →