Digital electronics interview questions, with worked answers, Verilog and numericals

• A latch is level-sensitive. While its enable is active it is transparent, so the output follows the input; when the enable goes inactive it holds the last value.
• A flip-flop is edge-triggered. It samples the input only at the clock edge and holds that value for the whole cycle. A D flip-flop is usually two latches back to back (master and slave) on opposite clock phases.

Flip-flops give one sampling instant per cycle, so timing analysis is simple and glitches on the data path between edges don't matter. Latches are smaller and allow time borrowing, which is why they appear on purpose in clock-gating cells and some high-speed paths.

With two's complement, the same adder handles signed and unsigned numbers, subtraction is just A + (~B + 1), and there is only one zero. Sign-magnitude and one's complement both have a +0 and a −0 and need extra logic for subtraction.

• An n-bit number ranges from −2ⁿ⁻¹ to 2ⁿ⁻¹ − 1: −128 to +127 for 8 bits.
• Signed overflow happens when two operands of the same sign give a result of the other sign. In hardware: V = carry into the MSB XOR carry out of the MSB.
• Unsigned overflow is simply the carry out of the MSB.

Example in 8 bits: 100 + 50 = 0110 0100 + 0011 0010 = 1001 0110, which reads as −106. Two positives gave a negative, so V = 1.

A gate is universal if any Boolean function can be built using only that gate. NAND and NOR each can produce NOT plus either AND or OR, and that set is functionally complete.

NOT : Y = (A·A)'                     → 1 NAND
AND : Y = ((A·B)')'                  → 2 NANDs (NAND, then NAND as inverter)
OR  : Y = (A'·B')' = A + B           → 3 NANDs (invert each input, then NAND)

Universality matters in practice because NAND is the fastest, smallest 2-input gate in CMOS, so standard-cell libraries and early logic families were built around it.

Gray code is an ordering of binary values in which consecutive values differ in exactly one bit. Converting is a single XOR per bit:

binary → Gray : g = b ^ (b >> 1)          1011 → 1110
Gray → binary : b[MSB] = g[MSB], then
                b[i] = b[i+1] ^ g[i]      1110 → 1011

• Rotary and position encoders: a reading taken mid-transition is off by at most one step, never a wild value.
• Async FIFO pointers: only one bit changes per increment, so synchronising the pointer into another clock domain is safe.
• K-maps: rows and columns use Gray order so neighbouring cells differ in one variable.
• Low power: fewer bit toggles per count than binary.

Setup time is how long the data must be stable before the clock edge; hold time is how long it must stay stable after it. Together they form a small window around the edge where the input must not change.

Physically, the master latch inside the flip-flop needs time for the new value to propagate through its internal path before it closes (setup), and the closing transmission gate needs time to turn fully off before the input moves (hold). Change inside the window and the internal node can be left mid-way, which is metastability.

setup: t_cq + t_logic,max + t_su  ≤  T + t_skew − t_jitter
hold : t_cq,min + t_logic,min     ≥  t_h + t_skew

Note that the clock period T appears only in the setup check.

• Moore: outputs depend only on the current state. They change only after a clock edge, so they're glitch-free when decoded from registered state, but react one cycle later.
• Mealy: outputs depend on the current state and the inputs. They can respond in the same cycle and usually need fewer states, but an input glitch can pass straight to the output.

A common compromise is a Mealy machine whose outputs are registered: it keeps the smaller state count and gets clean outputs, at the cost of one cycle of latency, which makes it behave like a Moore machine at the output.

Use A and B as the select lines and express each data input as a function of C:

So a 2ⁿ:1 multiplexer plus an inverter implements any function of n + 1 variables. Choosing different select variables changes how simple the data inputs are, so try the variable that appears least.

In a ripple-carry adder, each full adder waits for the carry from the one below it, so delay grows linearly with width: an n-bit add takes about n carry delays.

Carry lookahead computes every carry directly from two per-bit signals:

G_i = A_i · B_i          (this bit generates a carry)
P_i = A_i ⊕ B_i          (this bit propagates an incoming carry)
C1 = G0 + P0·C0
C2 = G1 + P1·G0 + P1·P0·C0
C3 = G2 + P2·G1 + P2·P1·G0 + P2·P1·P0·C0

All carries come out of two levels of logic instead of a chain. The cost is fan-in and area, which grow quickly, so real adders use 4-bit lookahead blocks combined hierarchically, or prefix adders (Kogge–Stone, Brent–Kung) with O(log n) delay.

Take B = C = 1 and let A fall from 1 to 0. Logically F = 1 throughout. In the circuit, AB turns off when A falls, but A'C only turns on after the inverter delay. For that brief moment both product terms are 0 and F dips: a static-1 hazard.

On the K-map, the two 1-cells ABC = 111 and 011 are adjacent but covered by different groups. Adding the consensus term BC covers both, so it holds F at 1 while A changes:

F = AB + A'C + BC      (BC is logically redundant but removes the hazard)

In synchronous design this glitch usually doesn't matter, because it settles before the next clock edge. It matters on anything sampled asynchronously: clocks, asynchronous resets, latch enables and outputs leaving the chip.

Give each state a meaning: how much of the pattern has been seen so far.

Two transitions carry the logic. From S2, another 1 stays in S2, because the last two bits are still "11". From S3, a 1 goes to S1, because that 1 could start the next match. Four states need two flip-flops in binary or four in one-hot.

module mod_n_counter #(parameter N = 10, W = $clog2(N)) (
  input  wire         clk, rst_n, en,
  output reg  [W-1:0] count,
  output wire         tc                // high on the last count
);
  assign tc = en && (count >= N-1);
  always @(posedge clk or negedge rst_n)
    if (!rst_n)   count <= {W{1'b0}};
    else if (tc)  count <= {W{1'b0}};
    else if (en)  count <= count + 1'b1;
endmodule

• For N = 10 the counter has 4 bits, so codes 10 to 15 are unused. A glitch or an upset could land the counter in one of them.
• Comparing with >= N-1 instead of == N-1 makes any unused state wrap to 0 on the next enabled clock, so the counter recovers on its own.
• tc lets counters cascade: the next stage counts only when this one wraps.

A blocking assignment (=) updates immediately, so the next line sees the new value. A non-blocking assignment (<=) evaluates all right-hand sides first and updates the targets together at the end of the time step, the way flip-flops all sample on one edge.

// non-blocking: a real 3-stage shift register
always @(posedge clk) begin q1 <= d;  q2 <= q1;  q3 <= q2; end

// blocking: every stage gets d on the same edge,
// so it behaves (and synthesises) like a single flop
always @(posedge clk) begin q1 = d;   q2 = q1;   q3 = q2;  end

• Use non-blocking in clocked always blocks.
• Use blocking in combinational always @(*) blocks.
• Don't mix both on the same variable, and don't assign one variable from two always blocks.

In a ripple counter each flip-flop is clocked by the previous one, so the bits change one after another. Going from 0111 to 1000, the outputs briefly pass through 0110, 0100 and 0000. A decoder looking for any of those values produces a short spike, and a block that reacts to edges or levels asynchronously sees a false trigger.

• Replace it with a synchronous counter, so all bits change on the same edge.
• Register the decoded output so only the settled value is used.
• Or use a code with one change per step (Gray or Johnson) so decoding can't glitch.

• A failure that goes away when you slow the clock is a setup problem: some path is longer than the period allows. Find the critical path, then pipeline it, simplify the logic or retime.
• A failure that stays at any frequency points to a hold problem (data racing through a short path when clock skew is large) or to a functional bug, such as a missing reset, an asynchronous input with no synchroniser, or an uninitialised state.

To tell them apart: check the timing report for both setup and hold, check that every clock and input delay is constrained, and look for paths between unrelated clocks. Changing frequency is a quick diagnostic, but not a fix for hold.

A latch is inferred whenever some path through an always @(*) block leaves an output unassigned, so the tool must remember its old value.

always @(*) begin
  y = 1'b0;                  // default first: every path assigns y
  case (sel)
    2'd0: y = a;
    2'd1: y = b;
    2'd2: y = c;
    default: y = 1'b0;       // covers sel = 3 and X in simulation
  endcase
end

• Every if needs an else, or a default assignment at the top.
• Every case needs a default, or full coverage of all values.
• Every output of the block must be assigned in every branch, not only the main one.

The enable comes from logic clocked on the same clock, so it changes shortly after the rising edge, while the clock is high. With gclk = clk & en, an enable that rises or glitches during the high phase creates a short extra pulse on the gated clock, and the register counts it.

The standard fix is an integrated clock-gating cell: a latch that is transparent while the clock is low captures the enable, and the AND uses the latched enable. The enable can only change while the clock is low, so the gated clock is always a whole, clean pulse.

On FPGAs, avoid gating clocks in logic at all: use the flip-flop's clock-enable pin or a dedicated clock buffer with enable.

A CMOS input has almost no DC current, so a floating pin drifts with leakage, coupling and noise and often settles near the middle of the supply. At that voltage both the PMOS and NMOS of the input stage are partly on, so current flows straight from V_DD to ground: extra power and heat. The input also wanders across the threshold, so the logic it drives toggles at random.

• Tie unused inputs to V_DD or ground, directly or through a resistor, depending on the gate's function.
• Use on-chip pull-ups or pull-downs where they exist.
• Never leave a used input undriven during reset or power-up.

The state register has codes that aren't real states: 3 bits for 5 states leaves 3 unused codes, and one-hot has many more. If power-up or noise leaves the register in one of them and the next-state logic has no way out, the FSM is stuck.

• Make sure reset reaches the state register, is long enough, and is released synchronously.
• Add a default branch that sends any illegal code to a known state.
• Check that synthesis didn't drop that recovery logic as unreachable. Tools often have a "safe FSM" option for exactly this.
• For one-hot, add a check that exactly one bit is set, and recover if not.