VLSI interview questions, by domain, role and depth

A flop sampling a changing input can hang at an intermediate level and resolve late. You can't eliminate it, but synchronizers (two or more flops) give it time to resolve, raising the mean time between failures exponentially.

Use a mod-3 counter clocked on the rising edge, generate a signal that is high for part of the count, and combine it with a copy delayed by a negative-edge flop (OR or AND them) to stretch the high time to 1.5 cycles.

Non-blocking (<=) in clocked always blocks, so all flops update together; blocking (=) in combinational always blocks. Mixing them in one block is a common source of simulation–synthesis mismatch.

Separate read and write clocks, binary pointers converted to Gray code, Gray pointers synchronized across domains with two-flop synchronizers, and full/empty computed from the synchronized pointers with an extra MSB to tell them apart.

Turning off the clock to registers that don't need to update, using an integrated clock-gating cell with a latch so the gated clock is glitch-free. It cuts dynamic power, often the largest power component.

Setup is how long data must be stable before the capturing clock edge; hold is how long it must stay stable after. Violating either can make the flop capture the wrong value or go metastable.

Positive skew (capture clock later) helps setup but hurts hold; negative skew does the opposite. That's why skew is balanced in CTS and why useful skew is applied carefully.

Draw each side on its own, then keep the Fermi level flat across the junction, because no current flows in equilibrium. The bands bend by qV_bi across the depletion region, which forms the barrier that forward bias lowers and reverse bias raises.

Classes can't contain a static interface instance, so a virtual interface is a handle that points to the real interface in the module world. Drivers and monitors use it to drive and sample DUT pins.

Code coverage is measured automatically from the RTL (lines, branches, toggles). Functional coverage is written by you from the spec (covergroups, cross coverage) and shows whether the features that matter were exercised. You need both.

Build (top-down), connect, end_of_elaboration and start_of_simulation, then the time-consuming run phase (with sub-phases), followed by extract, check, report and final. Objections control when the run phase ends.

The driver pulls transactions from the sequencer and drives pins. The monitor passively watches pins, rebuilds transactions and broadcasts them through an analysis port to scoreboards and coverage.

Too many nets competing for routing in an area: dense cells, macro corners, high pin density. Fixes include cell padding, placement blockages, better macro placement and halos, and logic restructuring.

The voltage drop across the power grid's resistance as current flows. Cells see a lower supply, slow down and may fail timing. Fixes are a stronger grid, more straps or vias, and spreading out high-activity cells.

Output stays high while NMOS is off, falls steeply in the middle where both devices are saturated (the switching threshold), and stays low once PMOS turns off. The steep middle region gives noise margins.

Dynamic switching power (αCV²f), short-circuit power during transitions, and static leakage. Reduce them with clock gating and lower voltage, sharp slews, and high-Vt cells or power gating respectively.

They turn flip-flops into a shift register in test mode, so you can load any state and read out results. That makes internal logic controllable and observable, which ATPG needs to reach high fault coverage.

FPGAs are built around edge-triggered flops; inferred latches use LUT feedback, break timing analysis and are often unintended (an incomplete if/case in combinational logic).

A two-flop synchronizer is for a single-bit, slow-changing control signal. A FIFO (or handshake) is for multi-bit data or high-rate transfers where every word must arrive intact.

Two minutes: the problem, your specific contribution, the hardest technical decision and why you made it, the result, and what you'd do differently. Expect follow-ups on every claim.