DESIGN FOR TESTABILITY INTERVIEW PREP

575 DFT questions. Every one answered.

Fault models to first silicon in 26 chapters. Every answer is written the way you'd say it in an interview, with a tip for the follow-up. Includes 25 solved numericals, an annotated ATPG report and 30 debugging scenarios.

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550+ DFT Design for Testability Interview Questions ebook cover — VLSI Beginners
575
QUESTIONS, ALL ANSWERED
26
CHAPTERS IN 4 PARTS
25
SOLVED NUMERICALS
30
DEBUG SCENARIOS
THE PROBLEM

DFT interviews go far past "what is a scan chain?"

DFT is one of the most in-demand VLSI tracks, and the interviews are practical. You'll be asked to compute test time, explain why coverage is stuck at 94%, choose between LOC and LOS, trace the JTAG TAP state machine, or say why the scan chain fails on every die in first silicon.

Most DFT prep material stops at definitions. Scattered notes cover scan and stuck-at faults, then thin out exactly where interviews get harder: compression and X-masking, OCCs, MBIST repair, IJTAG, hierarchical test, diagnosis and the numbers behind test cost.

This book is organised as a learning path. Chapters 1–7 build the fresher core. Chapters 8–14 cover at-speed test, compression, BIST, memory test and IEEE test access. Chapters 15–23 cover SoC architecture, implementation and production. Chapters 24–26 train debugging and how to deliver your answers.

WHAT'S INSIDE

More than a question list

DFT interviews test four skills: explaining a structure, working out a number, reading a coverage report and debugging a failure. The book trains each one.

CONCEPTS

An answer and a tip for every question

Each of the 575 questions has a difficulty level, an interview-ready answer, and an Interview Tip: the follow-up question or common mistake the interviewer is listening for.

NUMERICALS

25 solved problems, step by step

Scan test time with and without compression, tester data volume, coverage from fault classes, Williams–Brown DPPM, yield, LFSR sequences, MISR aliasing, March test time, JTAG chain lengths and memory repair.

REPORTS

An annotated ATPG report

A real-format statistics report with eight numbered callouts, then 20 questions on fault classes (DT, PD, UD, AU, ND) and a systematic way to close coverage gaps.

ARCHITECTURE

Every block on a DFT schematic

Mux-D scan, OCCs and LOC/LOS, decompressors and compactors, PRPG–MISR LBIST, MBIST collars and BIRA/BISR, the TAP controller, SIBs and IEEE 1500 wrappers.

SILICON

Where senior rounds go

Hierarchical DFT and streaming scan, test power, test-mode STA, pattern simulation, chain and volume diagnosis, yield learning and ISO 26262 in-system test.

REVISION KIT

Built for the night before

A formula sheet with a fault-model table, a 30-question rapid-fire round, an IEEE standards quick reference, a glossary, a 7-day plan and a readiness checklist.

LOOK INSIDE

Read ten real pages before you buy

These are pages from the actual PDF, not mockups. Click any page to zoom in and read it in full.

Table of contents showing 26 chapters in four parts and four appendices, totalling 575 questions
PAGE 5Contents: all 26 chapters
Chapter 2 page on cell-aware test, fault collapsing, equivalence, dominance and NAND gate fault counts
CHAPTER 2Cell-aware test, fault collapsing
Chapter 3 page on scan design, mux-D scan flip-flops, shift and capture modes and the scan pattern sequence
CHAPTER 3Scan design, shift and capture
Chapter 5 opener on scan chain reordering and why scan shift paths are prone to hold violations
CHAPTER 5Scan reordering and shift hold
Chapter 7 page on ATPG fault classes, computing test coverage, and unused, tied and blocked faults
CHAPTER 7Fault classes and coverage
Chapter 10 opener with a STUMPS-style logic BIST diagram showing PRPG, scan chains, MISR and BIST controller
CHAPTER 10Logic BIST, with diagram
Chapter 15 page on INTEST and EXTEST modes, graybox models, scan pin allocation, test scheduling and TAM
CHAPTER 15Wrapped cores, TAM, scheduling
Chapter 17 opener on why test power exceeds functional power and how to reduce shift power
CHAPTER 17Shift and capture power
Chapter 20 page on scan chain diagnosis, physical failure analysis, volume diagnosis and layout-aware diagnosis
CHAPTER 20Chain and volume diagnosis
Chapter 24 page with debugging scenarios on intermittent failures, boundary-scan shorts, uncontrollable clocks and hierarchical retargeting
CHAPTER 24Debugging scenarios
HOW IT'S STRUCTURED

Four parts, from fault models to production test

The chapters follow the order DFT is built on a real chip: the fundamentals of scan and ATPG first, then at-speed test, compression, BIST and test access, then SoC architecture and production, and finally the interview itself.

PART I — TEST FUNDAMENTALS, SCAN & ATPG
What every fresher interview checks
CH 1–7Manufacturing test basics, fault models, scan design, scan insertion and DRC, X-sources, scan in physical design and test-mode timing, ATPG, fault classes and coverage debug
160QUESTIONS
PART II — AT-SPEED, COMPRESSION, BIST & ACCESS
The architecture behind modern test
CH 8–14Transition test, LOC, LOS and OCC, test compression, logic BIST, 25 solved numericals, memory test, MBIST and repair, JTAG (IEEE 1149.1), IJTAG (IEEE 1687) and core wrappers (IEEE 1500)
165QUESTIONS
PART III — SOC, IMPLEMENTATION & PRODUCTION
What separates juniors from seniors
CH 15–23Hierarchical DFT and SoC test architecture, clocks, resets and special cells, test power, test-mode timing, pattern simulation, diagnosis and yield learning, quality and automotive, analog and I/O test, tool flow and scripting
175QUESTIONS
PART IV — INTERVIEW PRACTICE
Rehearsing the real thing
CH 24–2630 scenario-based debugging questions, a 30-question rapid-fire round, and interview strategy for DFT roles, from fresher projects to experienced-hire stories
75QUESTIONS
TOTAL ACROSS 26 CHAPTERS + 4 APPENDICES 575 questions
DIFFICULTY SPLIT
138 Beginner: fundamentals every candidate must know379 Intermediate: expected with project exposure58 Advanced: architecture, silicon and senior depth
SEE ALL 26 CHAPTERS
#CHAPTERQUESTIONS
PART I · TEST FUNDAMENTALS, SCAN AND ATPG
01DFT and Manufacturing Test FundamentalsQ1–Q25
02Fault ModelsQ26–Q50
03Scan Design FundamentalsQ51–Q75
04Scan Insertion, Test Design Rules and X-SourcesQ76–Q95
05Scan Chains in Physical Design and Test-Mode TimingQ96–Q115
06ATPG FundamentalsQ116–Q140
07Fault Classes, Coverage Reports and Coverage DebugQ141–Q160
PART II · AT-SPEED, COMPRESSION, BIST AND TEST ACCESS
08At-Speed Testing: Transition, LOC, LOS and OCCQ161–Q185
09Test CompressionQ186–Q210
10Logic BISTQ211–Q230
11Numerical Problems with Step-by-Step SolutionsQ231–Q255
12Memory Testing, MBIST and RepairQ256–Q280
13Boundary Scan and JTAG (IEEE 1149.1)Q281–Q305
14IJTAG (IEEE 1687) and Core Test Wrappers (IEEE 1500)Q306–Q325
PART III · SOC ARCHITECTURE, IMPLEMENTATION AND PRODUCTION
15Hierarchical DFT and SoC Test ArchitectureQ326–Q345
16Clocks, Resets and Special Cells in DFTQ346–Q365
17Low-Power DFT and Test PowerQ366–Q385
18Test-Mode Timing and DFT ConstraintsQ386–Q405
19Pattern Simulation, Validation and DebugQ406–Q425
20Fault Diagnosis, Silicon Debug and Yield LearningQ426–Q445
21Test Flow, Quality Metrics and Automotive RequirementsQ446–Q465
22Analog, Mixed-Signal, I/O and Advanced Test TopicsQ466–Q485
23DFT Tool Flow, Files and ScriptingQ486–Q500
PART IV · INTERVIEW PRACTICE
24Scenario-Based Debugging QuestionsQ501–Q530
25Rapid-Fire Revision RoundQ531–Q560
26Interview Strategy for DFT RolesQ561–Q575
APPENDICES
ADFT Standards and Test Modes Quick Referencep. 143
BGlossary of DFT Termsp. 144
CFinal Interview Readiness Checklistp. 146
DA Final Wordp. 147
FROM THE BOOK

Five real questions, as printed

A fault-collapsing count, a coverage calculation, a compression numerical, an at-speed comparison and a first-silicon debugging scenario. Every question in the book has the same parts: a direct answer and an interview tip.

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Q40BEGINNER How many stuck-at faults does a 2-input NAND gate have before and after collapsing? Uncollapsed: 3 pins × 2 = 6 faults. Equivalence collapsing merges the two input SA0 faults with output SA1, leaving 4 faults: A-SA1, B-SA1, Z-SA0 and one representative of {A-SA0, B-SA0, Z-SA1}. Tip: Practise this for AND, OR, NAND, NOR and inverter. It's a quick and common question.
Q142BEGINNER · REPORT How is test coverage computed from fault classes? Test coverage = (DT + PD credit × PD) / (total faults − UD). Fault coverage uses all faults in the denominator. With the sample report: (1,183,470 + 0.5 × 2,950) / (1,262,300 − 41,000) ≈ 97.02% test coverage. Tip: Interviewers sometimes hand you a report and a calculator. Practise with the sample.
Q232INTERMEDIATE · NUMERICAL 100,000 flops move from 10 chains to 1,000 compressed chains, and patterns rise from 3,000 to 6,000. What happens to test time at 50 MHz? Cycles ≈ 6,001 × 100 + 6,000 = 606,100, so time ≈ 12.1 ms against 0.60 s uncompressed: about 50× faster, even though the pattern count doubled. Tip: This is the key compression insight: more patterns, but far fewer cycles.
Q165INTERMEDIATE Compare LOC and LOS. LOS usually gets higher transition coverage with fewer patterns, but needs an at-speed scan enable and can launch functionally impossible transitions (overtesting). LOC needs no at-speed SE and launches only reachable transitions, at the cost of lower coverage and more patterns. Most designs use LOC. Tip: Structure it on three axes: coverage, SE timing, overtesting.
Q502INTERMEDIATE · SCENARIO The scan chain test fails on every die in first silicon. Where do you start? It's systematic, so suspect setup rather than defects: test-mode entry, pad direction, scan pin mapping in the test program, reset and watchdog behaviour, PLL/OCC bypass for shift, and shift frequency. Lower the shift frequency, vary voltage, and compare with simulation of the exact tester pattern. Tip: "All dies fail = setup or design issue; some dies fail = defects."
INTERVIEW IN A WEEK?

The 7-day revision plan from the book

Answer each question aloud before reading the answer. Sketch the scan flop, the LOC waveform and the TAP state machine. Solve every Chapter 11 numerical on paper, then make up your own variations.

DAY 1Ch 1–3Test fundamentals, fault models, scan design
DAY 2Ch 4–7Scan DRC, physical scan, ATPG, coverage
DAY 3Ch 8–11At-speed, compression, LBIST, all 25 numericals
DAY 4Ch 12–14MBIST and repair, JTAG, IJTAG and IEEE 1500
DAY 5Ch 15–18Hierarchical DFT, clocks, test power, test timing
DAY 6Ch 19–23Simulation, diagnosis, production, advanced topics, tool flow
DAY 7Ch 24–26Scenario debugging, rapid-fire round, interview strategy
WHO THIS IS FOR

Useful wherever you're starting from

Students and freshers

Preparing for a first DFT interview. Start with Part I and the Chapter 11 numericals; fresher rounds test scan, ATPG and coverage hardest.

RTL, STA and PD engineers

Moving into DFT and need the test view of clocks, timing and layout: OCCs, shift hold, test-mode STA, scan reordering and test power.

Working DFT engineers

Revising before a job change or promotion round. Parts III and IV have the hierarchical, diagnosis, silicon-debug and experienced-hire questions.

Self-learners

Studying without a mentor? Every question is answered, with a tip for the follow-up, so you can check your own reasoning.

550+ STA Interview Questions ebook cover
PAIRS WELL WITH

550+ STA Interview Questions

621 answered questions on timing: setup and hold, SDC, exceptions, OCV and CPPR, MCMM and timing reports. DFT rounds keep coming back to timing (shift hold, OCC launch-to-capture, test-mode constraints), so the two books work well together.

See the STA ebook

550+ DFT Interview Questions

575 questions, 26 chapters, every one answered. Instant PDF download.

Get the ebook now
QUESTIONS ABOUT THE BOOK
Does this ebook include answers?

Yes. All 575 questions come with an answer written the way you should say it in an interview, plus a specific interview tip: the follow-up or common mistake that separates a good answer from a great one.

What format do I get, and how do I receive it?

A 147-page PDF, delivered as an instant download through Topmate right after checkout.

I'm a fresher. Is this too advanced for me?

No. Chapters 1 to 7 build the fresher core: test fundamentals, fault models, scan design, scan rules, ATPG and coverage. The difficulty rises gradually from there, and the rapid-fire round in Chapter 25 is all beginner level.

Which DFT tools does the book assume?

None in particular. Fault-class names and command syntax differ between EDA vendors, so the book uses tool-neutral terms and a generic ATPG report format. The concepts transfer to any commercial DFT flow.

Does it cover JTAG, IJTAG and memory BIST, or only scan and ATPG?

All of them. There are full chapters on MBIST and memory repair, IEEE 1149.1 boundary scan, IEEE 1687 IJTAG and IEEE 1500 core wrappers, logic BIST, compression, hierarchical SoC test, low-power test, diagnosis and automotive test.

Is there a free preview?

Yes. Ten real pages are on this page, and the free DFT Interview Questions page has 90+ sample questions, worked answers, solved numericals and a test-time calculator.

What's your refund policy?

Because this is a digital product delivered instantly, sales are generally final. If you hit a technical issue with your download, contact us within 7 days. See our Refund Policy for details.

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