ASIC design interview questions, with worked answers and solved numericals

1. Specification and architecture → a micro-architecture document: blocks, interfaces, clocks, power modes and PPA targets.
2. RTL design → synthesisable Verilog/SystemVerilog, plus the SDC and UPF that describe timing and power intent.
3. Verification (simulation, formal, lint, CDC) → signed-off RTL.
4. Synthesis with the cell libraries → a gate-level netlist; DFT insertion adds scan and BIST; equivalence checking proves the netlist matches RTL.
5. Physical design: floorplan, power grid, placement, clock tree, routing → a routed layout with extracted parasitics.
6. Sign-off: STA across corners, IR drop and EM, DRC/LVS, LEC again after ECOs → GDSII or OASIS to the foundry.
7. Silicon: fabrication, packaging, production test and bring-up.

Close with the loops: timing or congestion problems in physical design often go back to synthesis constraints or RTL, and every late change is re-verified.

A Liberty (.lib) file describes every cell for timing and power tools: its pins and function, delay and output slew as tables indexed by input slew and output load, setup and hold constraints for sequential cells, input pin capacitances, internal and leakage power, and design-rule limits such as maximum capacitance.

Cell behaviour changes with process, voltage and temperature, so the same library is characterised at many PVT corners: slow process at low voltage and high temperature, fast process at high voltage and low temperature, and others, sometimes for several threshold-voltage flavours and with on-chip-variation data (LVF/AOCV). Synthesis, placement and sign-off each pick the corners that matter for the check they run.

Physical information lives elsewhere: cell outlines and pin shapes are in LEF.

Together they cover function, transformation and timing, which is why none of them can be skipped. Gate-level simulation is the safety net for what falls between: reset and initialisation, X behaviour, asynchronous paths and constraint mistakes.

create_clock -name clk -period 2.0 [get_ports clk]
set_clock_uncertainty 0.10 [get_clocks clk]
set_input_delay  0.8 -clock clk [remove_from_collection [all_inputs] [get_ports clk]]
set_output_delay 0.8 -clock clk [all_outputs]
set_driving_cell -lib_cell BUFX4 [all_inputs]
set_load 0.02 [all_outputs]
set_false_path -from [get_ports rst_n]   ;# if reset is synchronised inside

The clock, its uncertainty, I/O delays and the electrical environment are the minimum. The things most often forgotten:

• Input and output delays: unconstrained I/O paths simply don't appear in reports, so they look clean.
• Driving cells and loads: without them, input slew and output load are ideal and the timing is optimistic.
• Generated clocks for any divider or clock mux inside the block.

Run a constraint check (“check_timing” or similar) for unconstrained endpoints before trusting any slack.

Manufacturing introduces defects: shorts, opens, bridging and weak transistors. Without DFT, the internal state of a chip with millions of flops can't be controlled or observed in reasonable test time, so defects escape to customers.

Scan insertion replaces ordinary flops with scan flops, which have a multiplexer selecting either the functional D input or a scan input, controlled by scan enable. The flops are stitched into chains. In test mode the tester shifts a pattern in, pulses one capture clock, then shifts the response out while shifting the next pattern in.

The netlist therefore gains scan muxes (a little delay and area on every flop), chain wiring, test-mode control, often compression logic, and lockup latches where chains cross clock domains. ATPG then generates patterns for stuck-at and transition faults, and memories get MBIST.

UPF (Unified Power Format, IEEE 1801) describes power intent separately from RTL: power domains, their supply nets, which domains can be switched off or run at different voltages, the legal power states and the strategies for crossing between domains.

• Power switches (header or footer cells) to cut supply to a domain.
• Isolation cells on outputs of a switchable domain, clamping them to a safe value while it's off.
• Level shifters on signals between domains at different voltages.
• Retention registers that keep selected state on an always-on supply during power-down.
• Always-on buffers for control signals that must pass through a switched region.

The same UPF drives power-aware simulation, synthesis, place-and-route and sign-off checks, so the intent is verified at every step.

• Study connectivity first. Use flylines or a dataflow view to see which logic talks to which memory and to which block pins.
• Push memories to the edges or corners, with pins facing the logic, so standard cells get a large contiguous region in the middle.
• Leave channels between memories wide enough for the signals and power straps that must pass, and add halos so cells aren't crammed against macro pins.
• Align the bus: place the memories and the logic they feed so the wide bus runs in a straight, short path, and assign block pins on the side facing their partners at the top level.
• Plan power: rings or straps around memories and enough grid over the logic area.
• Check early with trial placement for congestion and timing before committing.

1. Check it's real. Is the path constrained correctly, or is it a false or multicycle path missing from SDC? Are the clocks related as intended?
2. Read the path. Where is the delay: many logic levels, one slow cell, a long wire, high fan-out, or poor input slew?
3. Cheap physical fixes: upsize drivers, swap to lower-V_T cells (watching leakage), buffer long wires, move cells closer together.
4. Logic changes in the tool: restructuring, cloning high fan-out drivers, pin swapping so the late signal uses the faster input.
5. Useful skew, if the next stage has spare slack.
6. Go upstream if it's still failing: synthesis constraints, or an RTL change to retime or pipeline the logic.

The cost of each fix rises down the list, so try them in that order, and recheck hold and power after every change.

Hold violations mean data arrives too early, so the fix is to add delay only on the short path, and only after the clock tree is built, because skew dominates hold.

• Insert delay cells or buffers close to the capture flop's D pin, on the branch that only feeds the failing endpoint, so paths sharing the earlier logic aren't slowed.
• Check the setup slack of every path through the inserted delay at the slow corner. A path can fail hold at the fast corner and still have little setup margin at the slow one.
• Use cell downsizing or higher-V_T swaps on short paths where possible, which add delay without much area.
• Large clusters of hold violations usually mean a skew or constraint problem, such as a missing clock latency or an unbalanced tree, not something to fix one path at a time.

Through an agreed sign-off checklist, tracked on a dashboard:

• Function: verification sign-off (coverage, regressions, formal), gate-level simulation with SDF, power-aware simulation.
• Equivalence: RTL to final netlist, including after every ECO.
• Timing: zero violations at every sign-off corner and mode with SI, plus checks on transitions, capacitance and noise.
• Power integrity: static and dynamic IR drop and electromigration within limits.
• Physical: DRC, LVS, antenna, ERC and density clean, or every waiver reviewed and approved.
• Test: scan chains verified, coverage targets met, MBIST working.
• Low power: UPF checks clean on the final netlist.

Anything not clean needs a written waiver approved by the right owner. “Ready” is a review decision, not a single tool result.

• Maximum skew: small enough that hold fixing stays manageable and setup isn't eaten, but not so tight that the tree needs huge buffers and power. Often set per clock group.
• Insertion delay (latency): shorter latency means less on-chip variation between launch and capture paths, so less pessimism.
• Maximum transition on clock nets, usually tighter than for data, for sharp edges and less variation.
• Cells and layers: which buffers and inverters may be used, and which metal layers, often with double spacing or shielding against crosstalk.
• Exceptions: sink pins to ignore, balance points for macros, and clock-gating cells to keep near their flops.

Choose them from the timing budget (how much uncertainty the setup and hold checks already allow) and from power, since the clock tree is often the largest single consumer of dynamic power.

• The gate-level netlist, with DFT inserted and scan chain information (a scan DEF) so chains can be reordered after placement.
• The SDC for every mode, consistent with what synthesis used.
• The UPF as updated by synthesis.
• Library and technology files: the Liberty corners, LEF, and the technology and parasitic models.
• Reports: area, timing at synthesis corners, unconstrained paths, check results, and any don't-touch or size-only instructions.
• An equivalence check result from RTL to this netlist.
• Notes on known issues: hard paths, multicycle paths, macros, special clocks.

A clean, documented hand-off saves weeks of re-running and argument later.

Simulation and synthesis are seeing different inputs. Common causes:

• A tie-off at integration: a configuration input tied to 0 or 1 in the top level makes downstream logic constant for synthesis, while the block-level testbench drives it.
• The register's input depends only on its reset value and signals synthesis has proven constant.
• Its outputs are unloaded, so the tool removed it and reports it as constant or unused.
• A parameter or define differs between the simulation and synthesis file lists.

Check the synthesis log for the constant-propagation reason, trace the input cone, and compare file lists and parameters. If the register must survive, for example a debug or spare register, mark it don't-touch.

LEC proves the logic is the same; it doesn't check timing, initialisation or test-mode behaviour. Look at what it doesn't cover:

• X and reset: flops without reset start at X in gate-level simulation; RTL may have hidden that through X-optimism.
• Timing: with SDF annotated, a real setup or hold violation, a missing constraint or an unconstrained asynchronous path shows up as a failure.
• Testbench assumptions: probing internal RTL signal names that no longer exist, or driving inputs exactly on the clock edge.
• Mode settings: test-mode or power-control pins left floating in the gate-level testbench.

Rerun without SDF (zero-delay). If it passes, it's a timing or constraint problem; if not, it's X, initialisation or the testbench.

That's temperature inversion. At advanced nodes with low supply voltage, cells can be slower at low temperature. Cold improves mobility, which speeds transistors up, but it also raises the threshold voltage. When V_DD is close to V_T, the threshold effect wins, so the slowest corner is cold, not hot.

• Include both hot and cold slow corners in sign-off, as the foundry's corner set specifies.
• Check which corner each path is worst at; wire-dominated paths may still be worst hot, because metal resistance rises with temperature.
• Fix the failing paths at the corner where they fail; don't assume hot is always the worst case.

• Scan muxes add delay in front of every flop's D input, so every path that ends at a flop loses a little slack, which pushes marginal paths over the edge.
• Extra load: scan connections add fan-out to flop outputs (the Q pin also drives the next flop's scan input), slowing the functional path.
• Test-mode logic on clocks and resets (clock muxes, reset bypass) adds delay to clock paths and can change skew.
• Compression and wrapper logic adds cells near I/O.

Budget for this from the start: synthesise with scan-equivalent cells, or with DFT inserted during synthesis, so timing is measured on the real structure. Reorder scan chains after placement to keep scan wiring short, and make sure test-mode paths have their own constraints.

Don't simply waive it. A quasi-static signal, such as a configuration register written once at boot, can be safe, but only if the claim is true and stays true:

• Check how it's written: by software while the destination domain is held in reset or idle? Is that sequence documented and verified?
• Check that every bit changes together or that the receiving logic doesn't care about intermediate values.
• Declare it to the tool as a static or quasi-static signal through its constraint mechanism, rather than a blanket waiver, so the assumption is recorded and reviewed.
• Add an assertion in simulation that the signal never changes while the destination is active.

If the signal can change at runtime, it needs a real synchronisation scheme.

1. Check clocks and resets: is each IP actually receiving a running clock and released from reset, in the order its documentation requires, with the right polarity?
2. Check the address map: does the boot code reach the IP at the address the interconnect decodes? Overlapping or missing regions are common.
3. Watch the bus: find the last completed transaction. A hang usually means a transaction never got a response: a protocol mismatch (for example AXI versus AHB bridging), a slave that never asserts ready, or an access to an unmapped address with no error response.
4. Check tie-offs and parameters: configuration inputs, interrupt connections and data widths set at integration.

Protocol assertions or checkers on every interface turn this from a long debug into an immediate error message.