A hiring manager on a chip team spends well under a minute on a first pass. Here's a template built for that scan, a formula for bullets that sound like engineering, and a checklist of the mistakes that get resumes rejected.
In roughly this order. If these five aren't obvious at a glance, the rest of the page rarely gets read.
A headline like "Design Verification Engineer, SV/UVM" tells them straight away which pile you belong in.
Verilog, SystemVerilog, UVM, TCL, Python: the words they're matching against the job post.
Coverage reached, bugs found, frequency closed. For freshers, the project section does the job an experience section would.
An internship, a college tape-out, or hands-on time with commercial EDA tools. Any one of these stands out.
Still screened at many product companies for freshers. Put it near the top while you're under two years' experience.
A single column, standard headings, no graphics. A clean page reads as someone who writes clean RTL.
Amber highlights are placeholders to replace with your own details. The numbers are there to show the style, so use your real ones. Never copy a figure you can't defend.
Block-level PD engineer with 3 production tape-outs, owning netlist-to-GDS for CPU-subsystem blocks of up to 2.5M instances. Strongest in timing closure and CTS; looking to grow into sub-system ownership.
Headline → Education → Skills → Projects → Internship → Achievements
Headline → Summary → Experience → Skills → Education. Projects fold into experience.
Paste into Google Docs or Word, set an 11 pt font and 0.6″ margins, replace the placeholders, then export to PDF.
Each line should answer: what did you do, to what, how, and what changed because of it?
Built, verified, closed, reduced, automated, debugged. Not "worked on".
A UVM environment for an AXI4-Lite slave. A 2.5M-instance CPU block.
With constrained-random sequences and SVA. By reworking the CTS strategy.
96% functional coverage, 3 RTL bugs found. 35% less skew, 40 ps recovered.
Same experience, told in a way that gives an interviewer something to ask about.
Match the job post. Only list what you can explain under follow-up questions.
| DOMAIN | LANGUAGES & METHODS | CONCEPTS | PROJECT THAT PROVES IT |
|---|---|---|---|
| Design verification | SystemVerilog, UVM, SVA, Python | Constrained-random, functional coverage, scoreboards, RAL | UVM testbench for an AXI/APB peripheral with a coverage report |
| RTL design | Verilog, SystemVerilog, TCL | FSMs, pipelining, CDC, low-power, synthesis constraints | Pipelined processor core or a CDC-safe async FIFO |
| Physical design | TCL, Python | Floorplanning, CTS, MMMC, IR drop, ECOs | Open-source RTL-to-GDS (OpenROAD/OpenLane) with timing reports |
| STA | TCL, SDC | Setup/hold, OCV, false/multicycle paths, clock groups | Constraining and closing a multi-clock design |
| DFT | TCL, Verilog | Scan insertion, ATPG, fault models, MBIST, JTAG | Scan insertion + ATPG coverage on an open design |
| Analog / mixed-signal | SPICE, Verilog-A, MATLAB | Op-amps, bandgaps, PLLs, ADCs, noise, mismatch | A two-stage op-amp or bandgap with PVT simulation results |
| FPGA | Verilog/VHDL, TCL, C | Timing closure, IP integration, AXI, HLS | An accelerator on a dev board, with the resource usage report |
Tick each one once you've confirmed it's not on your resume. Your progress is saved in this browser only.