Verilog interview questions, with worked answers, code and output puzzles

always @(posedge clk) begin
  b <= a;
  c <= b;
  a <= c;
end
// a=1, b=2, c=3  ->  after one edge: a=3, b=1, c=2

Each non-blocking assignment reads its right-hand side when the statement runs, but the update is held back until every block woken by the edge has finished reading. All three registers therefore see the old values, exactly like three flip-flops sampling on the same edge.

With blocking assignments, b = a changes b at once, then c = b copies the new b, and a = c copies that too: all three end up holding the old a. Synthesis builds what the blocking code describes, which is not a rotation. So the rule is non-blocking in clocked blocks, blocking in combinational blocks, and never both on one variable.

• Z (high impedance) means nothing is driving the net: a released tri-state bus, an input port left unconnected, or a net that was declared but never driven. Seeing Z inside a block usually means a missing connection.
• X (unknown) means the simulator can't decide between 0 and 1: a variable that was never assigned (often a flop with no reset), two drivers fighting, a Z fed into logic, or an out-of-range array read.

X is a simulation idea. In silicon every node settles at 0 or 1; X says "we don't know which". An X that survives reset is therefore a design question, not a cosmetic one: the hardware will pick some value, and the design must not depend on which.

Most expressions are context-determined: the simulator finds the widest operand, including the left-hand side of the assignment, extends every operand to that width and then computes. With a 9-bit sum, a + b is computed at 9 bits and the carry survives.

reg [7:0] a = 8'd200, b = 8'd100;
reg [8:0] sum;
sum = a + b;     // 9-bit context: 300
sum = {a + b};   // braces are self-determined: 8 bits, 300 mod 256 = 44

A concatenation is self-determined: its operands keep their own width whatever the context. Other self-determined places are comparison operands, reduction operators, shift amounts and arguments to system tasks. Those are where carries quietly disappear.

reg en;              // never assigned: en = X
always @* begin
  if (en) y = a;     // condition is X: treated as false
  else    y = b;     // RTL sim reports y = b
end

An if treats an X or Z condition as false and takes the else branch. Simulation therefore shows a clean, believable value, while real hardware could select either input. This is called X-optimism: the X disappears instead of spreading, so the missing initialisation is never noticed.

Checks help: en === 1'bx in a testbench assertion compares X literally, and the conditional operator en ? a : b is more pessimistic, merging the two inputs bit by bit. The real fix is to give en a defined value, usually through reset.

casex treats X and Z bits as don't-care on both sides of the comparison. If the selector itself is X, for example because a register was never reset, the first item matches and simulation carries on with a believable result.

Write the wildcards with ? in a casez instead. The decoding is the same, but an X on the selector no longer matches a wildcard item, so it falls through to the default, where you can drive X or flag an error and actually see the problem.

• Depth → parameter. A parameter is a per-instance constant the parent can override: fifo #(.DEPTH(64)) u_fifo (...);
• Address width → localparam. It is derived inside the module and must not be overridden independently: localparam AW = $clog2(DEPTH);
• Debug switch → `define. A macro is plain text substitution that stays visible from the point it's read to the end of compilation, across files, so it suits global switches tested with `ifdef.

The trade-off is scope. Parameters and localparams belong to one instance and appear in the hierarchy; macros are global, and a later file can redefine one, so compile order can change the result.

module reg32_be (
  input  wire        clk, rst_n,
  input  wire [3:0]  be,          // one enable per byte
  input  wire [31:0] wdata,
  output reg  [31:0] q
);
  integer i;
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) q <= 32'd0;
    else
      for (i = 0; i < 4; i = i + 1)
        if (be[i]) q[8*i +: 8] <= wdata[8*i +: 8];
  end
endmodule

The loop unrolls into four independent byte registers, each with its own enable. The indexed part-select q[8*i +: 8] picks byte i with a variable start and a constant width. Bytes whose enable is low simply hold, which is what a flop with an enable does.

localparam IDLE = 2'd0, BUSY = 2'd1, DONE = 2'd2;
reg [1:0] state, nxt;
reg [1:0] cnt;

always @(posedge clk or negedge rst_n)        // state register
  if (!rst_n) state <= IDLE;
  else        state <= nxt;

always @* begin                               // next-state logic
  nxt = state;                                // default: stay
  case (state)
    IDLE: if (start)      nxt = BUSY;
    BUSY: if (cnt == 2'd2) nxt = DONE;
    DONE:                 nxt = IDLE;
    default:              nxt = IDLE;         // recover from 2'd3
  endcase
end

always @(posedge clk or negedge rst_n)        // cycle counter
  if (!rst_n)              cnt <= 2'd0;
  else if (state == BUSY)  cnt <= cnt + 2'd1;
  else                     cnt <= 2'd0;

assign busy = (state == BUSY);
assign done = (state == DONE);

The default assignment nxt = state; at the top of the combinational block means no path leaves nxt unassigned, so there's no latch. The default item sends the unused code back to IDLE. Outputs decoded from the state alone make this a Moore machine with glitch-free, registered-state outputs.

Describe a RAM the way the block RAM works: synchronous write, and a registered read address or registered read data.

module spram #(parameter AW = 10, DW = 16) (
  input  wire          clk, we,
  input  wire [AW-1:0] addr,
  input  wire [DW-1:0] din,
  output reg  [DW-1:0] dout
);
  reg [DW-1:0] mem [0:(1<<AW)-1];
  always @(posedge clk) begin
    if (we) mem[addr] <= din;
    dout <= mem[addr];          // registered read: maps to BRAM
  end
endmodule

Things that push synthesis back to flip-flops or LUT RAM: an asynchronous read (assign dout = mem[addr];), a reset on the memory array, more read or write ports than the primitive has, or reading every location at once in a loop. Check the synthesis report for the inferred RAM type; don't assume.

// Latch: y is not assigned when sel == 2'b11
always @* begin
  case (sel)
    2'b00: y = a;
    2'b01: y = b;
    2'b10: y = c;
  endcase
end

// Fix 1: default assignment first, then override
always @* begin
  y = 1'b0;
  case (sel)
    2'b00: y = a;
    2'b01: y = b;
    2'b10: y = c;
  endcase
end

// Fix 2: cover every value
    default: y = 1'b0;   // added as the last case item

When sel is 2'b11, no branch assigns y, so it has to keep its old value, and only a latch can do that. A default assignment at the top of the block covers every path for every output at once, which is why many teams make it a rule. Confirm with the lint and synthesis logs, which both list inferred latches.

module delay_line #(parameter W = 8, N = 4) (
  input  wire         clk,
  input  wire [W-1:0] din,
  output wire [W-1:0] dout
);
  wire [W-1:0] stage [0:N];
  assign stage[0] = din;
  genvar k;
  generate
    for (k = 0; k < N; k = k + 1) begin : g_stage
      reg [W-1:0] r;
      always @(posedge clk) r <= stage[k];
      assign stage[k+1] = r;
    end
  endgenerate
  assign dout = stage[N];
endmodule

The array has N + 1 entries so that each stage has an input and an output. Each loop iteration declares its own register inside the named block, giving stable names such as g_stage[2].r for waveforms and timing constraints. In an FPGA, a delay line with no reset like this one can map into shift-register LUTs instead of separate flops.

module stretch #(parameter N = 4) (
  input  wire clk, rst_n, pulse,
  output wire out
);
  localparam CW = $clog2(N + 1);
  reg [CW-1:0] cnt;
  always @(posedge clk or negedge rst_n)
    if (!rst_n)      cnt <= {CW{1'b0}};
    else if (pulse)  cnt <= N;            // (re)start on every pulse
    else if (cnt != 0) cnt <= cnt - 1'b1;
  assign out = (cnt != 0);
endmodule

The counter is sized with $clog2(N + 1) so it can hold N itself. A new pulse during the stretch restarts the count, so pulses close together merge into one longer output; say that out loud, because interviewers often ask what should happen in that case. The output is decoded from a register, so it's glitch-free.

Verilog creates an implicit 1-bit wire for any undeclared identifier used in a port connection or on the left of a continuous assignment. The misspelt name became a new, undriven net, so the instance sees Z (or X after logic), and the real signal is left unconnected. If the real signal was a bus, the implicit net is only one bit wide, which adds width-mismatch warnings that are easy to miss.

• Put `default_nettype none at the top of every RTL file, so any undeclared name is a compile error. Restore `default_nettype wire at the end if third-party code relies on the default.
• Read lint warnings for "undriven net" and "port width mismatch".

The sum of four 8-bit values needs 10 bits (up to 1,020). If the sum is held in an 8-bit variable, or computed in a self-determined context, the top bits are lost before the divide.

reg [7:0] s0, s1, s2, s3, avg;
reg [9:0] sum;
always @(posedge clk) begin
  sum <= s0 + s1 + s2 + s3;   // 10-bit context: no overflow
  avg <= sum[9:2];            // divide by 4 = drop two bits
end

Work out the worst-case width first: adding N values of W bits needs W + ceil(log2 N) bits. Then check every intermediate variable and every concatenation along the path, since one narrow temporary is enough to break it.

reg [4:0] i;                 // 5 bits: holds 0 to 31
always @* begin
  ones = 0;
  for (i = 0; i < 32; i = i + 1)   // i never reaches 32
    ones = ones + data[i];
end

A 5-bit index wraps from 31 back to 0, so i < 32 is always true and the loop never exits. Synthesis unrolls the loop using the constant bounds, so it may produce correct hardware, which makes the bug look like a simulator problem.

Use an integer index (32-bit signed), or make the index one bit wider than the highest value it must compare against.

count is declared reg [7:0], which is unsigned. An unsigned value is always greater than or equal to zero, so the condition is always true. When the counter decrements past 0 it wraps to 255 and keeps going.

• Test for the terminal value directly: while (count != 0), or check before decrementing.
• Or declare the variable signed or use integer, and make sure every operand in the comparison is signed, since one unsigned operand makes the whole comparison unsigned.

Lint tools flag this as a "comparison is always true" warning, which is a good reason to read lint output carefully.

ASIC synthesis ignores initial blocks, so the real flops have no reset value. RTL simulation starts the counter at 0 and hides that. Two problems follow:

• Gate-level simulation starts every flop at X. The counter stays X forever, because X + 1 is X, and everything downstream turns X.
• Silicon powers up with a random count, so the first outputs are unpredictable.

Fix it by adding a real reset to the register (or proving the value doesn't matter and documenting it). Many teams also run RTL simulation with random initial values, or with initialisation turned off, to expose missing resets early. FPGA flows are different: there, an initial value can set the bitstream's power-up state, but it still doesn't act as a reset you can reapply.

always @(a or b)          // c is missing
  y = (a & b) | c;

In RTL simulation the block only wakes up when a or b changes. A change on c alone leaves y stale until the next change on a or b, so the waveform looks like a register. Synthesis ignores sensitivity lists and builds plain combinational logic, so the netlist responds to c immediately. The two no longer match.

• Use always @*, which builds the list from everything the block reads.
• Lint reports incomplete sensitivity lists; treat that warning as an error.