A one-page quick reference for core Verilog syntax — data types, procedural blocks, module instantiation, and synthesis-safe constructs.
A printable, single-page version of this reference.
wire for continuous assignments and combinational connections; reg for values assigned inside procedural blocks (always/initial) — it doesn't always mean a physical register.
always blocks execute repeatedly on sensitivity-list triggers, used for both combinational and sequential logic. initial blocks execute once, used mainly in testbenches.
Prefer named port mapping (.clk(clk)) over positional mapping — it's more readable and safer against port-order changes.
parameter can be overridden at instantiation; localparam cannot — use it for values derived from other parameters that shouldn't be independently overridden.
Avoid #delay statements, initial blocks (outside testbenches), and unconstrained for loops in RTL meant for synthesis.
Use generate/endgenerate with for or if to instantiate repeated or conditional hardware structures at compile time.
This cheat sheet covers the essentials. The free Verilog question bank has 90+ questions with worked answers, and the ebook has 580, all answered.
See Verilog questions