UVM interview questions, with code answers, solved problems and a real UVM log read line by line

• Components are the permanent structure: they're built once in build_phase, have a parent and a place in the hierarchy, take part in every phase, and live for the whole simulation (driver, monitor, agent, env, test).
• Objects are data: created and discarded freely at run time, with no parent and no phases (sequence items, sequences, config objects, register models).

class bus_item extends uvm_sequence_item;            // object
  `uvm_object_utils(bus_item)
  function new(string name = "bus_item");
    super.new(name);
  endfunction
endclass

class bus_driver extends uvm_driver #(bus_item);     // component
  `uvm_component_utils(bus_driver)
  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction
endclass

1. build: create children and read configuration. Top-down, because a parent must exist and set configuration before its children are created.
2. connect: wire TLM ports. Bottom-up, though any order would work once everything exists.
3. end_of_elaboration: final checks and topology printing.
4. start_of_simulation: last setup before time starts.
5. run (a task, with the parallel runtime sub-phases reset, configure, main, shutdown): stimulus, driving, monitoring, checking.
6. extract, check, report, final: collect results, check leftovers such as unmatched scoreboard entries, print summaries.

create() asks the factory for an object. If a test has registered an override, the factory returns the replacement class instead; new() always builds exactly the class named in the code.

// in the agent
drv = bus_driver::type_id::create("drv", this);

// in a test's build_phase, before the env is built
bus_driver::type_id::set_type_override(err_driver::get_type());        // everywhere
bus_driver::type_id::set_inst_override(err_driver::get_type(),
                                       "env.agt0.drv", this);           // one instance

The replacement must extend the original class and be registered with `uvm_component_utils. Instance overrides take priority over type overrides.

The top module, which owns the real interface instance, puts a handle into the config DB; the driver (and monitor) fetch it in build_phase.

// tb_top
initial begin
  uvm_config_db#(virtual bus_if)::set(null, "uvm_test_top.env.agt*", "vif", bus0);
  run_test();
end

// driver build_phase
if (!uvm_config_db#(virtual bus_if)::get(this, "", "vif", vif))
  `uvm_fatal("NOVIF", "virtual interface not set for this agent")

Better still, put the handle in the agent's config object, so all of an agent's settings travel together.

// sequence
task body();
  repeat (10) begin
    req = bus_item::type_id::create("req");
    start_item(req);                     // 1. wait for the sequencer to grant
    if (!req.randomize() with { kind == WRITE; })
      `uvm_error("RAND", "randomize failed")
    finish_item(req);                    // 2. hand over; wait for item_done
  end
endtask

// driver
task run_phase(uvm_phase phase);
  forever begin
    seq_item_port.get_next_item(req);    // 3. blocks until an item is granted
    drive(req);                          // 4. wiggle pins via the vif
    seq_item_port.item_done();           // 5. releases finish_item
  end
endtask

Randomising between start_item and finish_item means the item reflects the latest state (late randomisation). For a response, the driver sets the ID with rsp.set_id_info(req) and the sequence calls get_response().

An active agent drives the interface (sequencer, driver and monitor); a passive agent only observes (monitor alone). The same agent class is used both ways, controlled by configuration.

function void build_phase(uvm_phase phase);
  super.build_phase(phase);
  mon = bus_monitor::type_id::create("mon", this);
  if (get_is_active() == UVM_ACTIVE) begin
    sqr = bus_sequencer::type_id::create("sqr", this);
    drv = bus_driver   ::type_id::create("drv", this);
  end
endfunction

function void connect_phase(uvm_phase phase);
  if (get_is_active() == UVM_ACTIVE)
    drv.seq_item_port.connect(sqr.seq_item_export);
endfunction

Passive agents matter for reuse: at SoC level the real block drives the bus, and your agent just watches and feeds the scoreboard.

`uvm_analysis_imp_decl(_exp)
`uvm_analysis_imp_decl(_act)

class bus_sb extends uvm_scoreboard;
  `uvm_component_utils(bus_sb)
  uvm_analysis_imp_exp #(bus_item, bus_sb) exp_imp;
  uvm_analysis_imp_act #(bus_item, bus_sb) act_imp;
  bus_item expq[$];

  function new(string name, uvm_component parent);
    super.new(name, parent);
    exp_imp = new("exp_imp", this);
    act_imp = new("act_imp", this);
  endfunction

  function void write_exp(bus_item t);  expq.push_back(t);  endfunction

  function void write_act(bus_item t);
    bus_item e;
    if (expq.size() == 0) begin `uvm_error("SB/UNEXP", t.convert2string()) return; end
    e = expq.pop_front();
    if (!t.compare(e))
      `uvm_error("SB/MISMATCH", $sformatf("exp %s got %s", e.convert2string(), t.convert2string()))
  endfunction

  function void check_phase(uvm_phase phase);
    if (expq.size()) `uvm_error("SB/LEFT", $sformatf("%0d expected items never seen", expq.size()))
  endfunction
endclass

In the env: ref_model.ap.connect(sb.exp_imp); out_mon.ap.connect(sb.act_imp);. The same monitor port can also connect to a coverage subscriber.

Each run-time phase keeps a count of raised objections. It ends when the count returns to zero (plus any drain time). If nobody raises one, the phase ends at time 0 and nothing runs.

task run_phase(uvm_phase phase);
  bus_seq seq = bus_seq::type_id::create("seq");
  phase.raise_objection(this, "main traffic");
  seq.start(env.agt.sqr);
  phase.get_objection().set_drain_time(this, 200ns);   // let the last items reach the scoreboard
  phase.drop_objection(this, "main traffic");
endtask

Raise in the test or the top-level sequence, not in drivers and monitors that run forever; and not per transaction, which slows large simulations.

A virtual sequence doesn't generate items itself; it coordinates sequences on several agents. It usually runs on a virtual sequencer that holds handles to the real sequencers, reached through p_sequencer.

class top_vseq extends uvm_sequence;
  `uvm_object_utils(top_vseq)
  `uvm_declare_p_sequencer(top_vsqr)       // top_vsqr has apb_sqr and axi_sqr handles
  function new(string name = "top_vseq"); super.new(name); endfunction

  task body();
    apb_cfg_seq  cfg = apb_cfg_seq ::type_id::create("cfg");
    axi_traffic  trf = axi_traffic ::type_id::create("trf");
    cfg.start(p_sequencer.apb_sqr);         // configure the DUT first
    trf.start(p_sequencer.axi_sqr);         // then send traffic
  endtask
endclass

The env sets the sequencer handles in the virtual sequencer during connect_phase. Some teams skip the virtual sequencer and pass handles straight into the sequence; either is fine if it's consistent.

uvm_status_e   st;
uvm_reg_data_t v;
regmodel.ctrl.write(st, 32'h11);         // front door: a real bus transaction via the adapter
regmodel.ctrl.read (st, v);
regmodel.ctrl.peek (st, v);              // back door: direct HDL access, no bus, zero time
regmodel.ctrl.enable.set(1'b1);          // change the desired value only
regmodel.ctrl.update(st);                // write it if desired differs from mirrored
regmodel.ctrl.mirror(st, UVM_CHECK);     // read the DUT and compare with the mirror

• Front door checks the bus path and decoding; it's what software will do.
• Back door is fast for setup and for checking values a bus can't read.
• Mirror is the model's best guess of the DUT's value; a predictor keeps it in sync from bus monitor traffic.

• Factory override: replace a whole class for a test (an error-injecting driver). Simple, but only one replacement per instance, and you copy or extend the whole class.
• Callback: insert extra behaviour at hooks the component author provided, without replacing it. Several callbacks can be stacked and added or removed at run time.

class drv_cb extends uvm_callback;
  virtual task pre_drive(bus_driver d, bus_item t); endtask
endclass

// in bus_driver
`uvm_register_cb(bus_driver, drv_cb)
...
`uvm_do_callbacks(bus_driver, drv_cb, pre_drive(this, req))
drive(req);

// in a test: corrupt every 10th item
uvm_callbacks #(bus_driver, drv_cb)::add(env.agt.drv, my_err_cb);

`uvm_info("DRV", $sformatf("sent %s", req.convert2string()), UVM_HIGH)

// command line: +UVM_VERBOSITY=UVM_HIGH        (show HIGH and below)
//               +UVM_MAX_QUIT_COUNT=10         (stop after 10 errors)

// demote one known, waived error in one test
env.sb.set_report_severity_id_override(UVM_ERROR, "SB/LEN", UVM_WARNING);

// silence one noisy ID
env.agt.mon.set_report_id_action("MON/IDLE", UVM_NO_ACTION);

Verbosity filters only `uvm_info; warnings, errors and fatals always print unless their action is changed. Good message IDs make logs searchable and let you control one message without touching others.

1. No objection raised: nobody raised one in run_phase (or the sequence was started in a sub-phase that nobody objected to), so the phase ended immediately.
2. Raised in the wrong phase: an objection in main_phase doesn't keep run_phase alive, and the reverse.
3. Sequence never started: no start() call, or started on a null sequencer handle (passive agent, wrong path).
4. Wrong test: +UVM_TESTNAME misspelt, so the base test with no stimulus ran.

Turn on +UVM_OBJECTION_TRACE and check the "Running test" line at the top of the log.

• Created with new(): the factory never sees it. Every overridable class must be created with type_id::create().
• Override set too late: after super.build_phase() built the env, or in connect_phase.
• Wrong path for an instance override: paths are relative to the context argument; print the full name with get_full_name().
• Not registered: the replacement lacks `uvm_component_utils, or a string-based override names a type that doesn't exist (a warning, easy to miss).
• Not a subclass: the replacement must extend the original type.

factory.print() and uvm_top.print_topology() answer most of these in seconds.

1. Run with +UVM_CONFIG_DB_TRACE: it prints every set and get, with paths and field names.
2. Path: the instance path in set() must match the getter's full name (wildcards included); compare against get_full_name().
3. Field name: "vif" vs "m_vif"; it's a plain string match.
4. Type: the parameter of uvm_config_db#(T) must be identical on both sides.
5. Order: the set must happen before the get; a set in the top module after run_test() is too late.

• Monitor sampling: sampling on the wrong edge, without the clocking block, or before a valid/ready handshake completes.
• Shared objects: the monitor reuses one transaction object and the scoreboard stores the handle, so earlier entries change.
• Ordering: the DUT is allowed to reorder (by ID or priority) and the scoreboard compares in strict order.
• Reference model: the model is wrong, or uses a different configuration from the DUT.
• Compare method: do_compare includes a field that shouldn't be compared (a timestamp) or skips one that should.

Print both transactions at the failing time and compare them to the waveform field by field.

• An objection never dropped: a path through the code that returns early, or an exception, skips the drop. +UVM_OBJECTION_TRACE shows who still holds it.
• Driver handshake: item_done() not called, so finish_item() never returns.
• Responses: the sequence waits in get_response() for a response the driver never sends.
• Waiting on the DUT: the driver waits for a ready or ack that never comes; add a timeout inside the driver that reports what it was waiting for.
• Locked sequencer: a sequence called lock() or grab() and never released it.

• Usually passive: another block drives the bus, so the agent becomes a monitor plus checks.
• Configuration, not code: active or passive, virtual interface, address ranges and checks come from the agent's config object.
• Paths: config DB paths and instance overrides change with the new hierarchy, so avoid hard-coded full paths in the agent.
• Scoreboard and coverage: block-level end-to-end checks may still apply; some move into a subsystem scoreboard.
• Sequences: block sequences can be layered under a virtual sequence if the agent stays active somewhere.

If the agent needs code changes to move up a level, say what you'd fix in its design so the next reuse needs none.