ROADMAP
Design verification engineer
Prove the chip works before it's built.
Suits: People who like programming, debugging and breaking things. It's the largest hiring area for freshers.
3–4 wks1. Digital logic and Verilog
Combinational/sequential logic, FSMs, Verilog RTL and simple testbenches.
MILESTONEAn exhaustively tested adder and a counter with self-checking testbenches. 4–6 wks2. SystemVerilog for verification
Classes, inheritance, polymorphism, randomization and constraints, queues, mailboxes, interfaces and clocking blocks.
MILESTONEA class-based testbench for a FIFO with a reference model. 4–6 wks3. UVM
Components, phases, factory, config DB, sequences, TLM and scoreboards.
MILESTONEA full UVM environment for a simple bus peripheral (APB or a register block). 3–4 wks4. Coverage and assertions
Covergroups, crosses, coverage closure, SVA properties and bind.
MILESTONEA coverage report reaching your goals, plus protocol assertions. ongoing5. Protocols and interview practice
AXI/APB/AHB basics, debug stories, mock interviews.
MILESTONEYour project on GitHub with a README and results. RTL / design engineer
Turn a specification into synthesizable hardware.
Suits: People who enjoy architecture, logic and making hardware fast and small. M.Tech graduates are often preferred.
3–4 wks1. Digital logic and Verilog
Gates to FSMs, and synthesizable coding style.
MILESTONEA tested counter, shift register and sequence detector. 4–6 wks2. Micro-architecture
Datapaths, pipelining, FIFOs, arbiters, handshakes (valid/ready) and memories.
MILESTONEA synchronous FIFO and a round-robin arbiter with testbenches. 3–4 wks3. Timing and CDC
Setup/hold, critical paths, synchronizers, async FIFOs and reset strategy.
MILESTONEAn asynchronous FIFO with Gray pointers. 3–4 wks4. Synthesis and low power
The synthesis flow, constraints, area/timing trade-offs, clock gating and UPF basics.
MILESTONESynthesize your design (open-source Yosys) and read the reports. ongoing5. Projects and interviews
A small processor or accelerator, lint and CDC awareness, design reviews.
MILESTONEA pipelined RISC-V core or a UART with FIFOs, documented on GitHub. Physical design engineer
Turn a netlist into a manufacturable layout that meets timing.
Suits: People who like optimization, tools and scripting, and seeing the physical side of chips.
2–3 wks1. Basics
CMOS, digital logic, and enough RTL to read a netlist.
MILESTONEExplain every stage of the ASIC flow from memory. 4–5 wks2. STA
Setup/hold, timing paths, SDC constraints, corners, OCV and reading timing reports.
MILESTONEConstrain and analyse a small design with OpenSTA. 4–6 wks3. Floorplan, placement and CTS
Macro placement, power planning, congestion, clock tree goals and hold fixing.
MILESTONERun an open-source RTL-to-GDS flow (OpenROAD/OpenLane) on a small core. 3–4 wks4. Routing and sign-off
Routing, crosstalk, DRC/LVS, IR drop, EM and ECOs.
MILESTONEClose timing and DRC on your OpenLane run, and write up what you changed. ongoing5. Scripting and interviews
TCL and Python for reports and automation.
MILESTONEA script that parses a timing report into a summary. DFT engineer
Make sure every manufactured chip can be tested.
Suits: People who like systematic, rules-driven work that touches the whole design.
2–3 wks1. Basics
Digital logic, basic RTL literacy and flip-flop behaviour.
MILESTONEExplain why testing internal logic from the pins is hard. 3–4 wks2. Scan design
Scan flops, chains, shift/capture, test clocks and scan rules.
MILESTONEHand-draw scan insertion for a small circuit. 3–4 wks3. Fault models and ATPG
Stuck-at, transition, at-speed (LOC/LOS), fault coverage and compression.
MILESTONECompute stuck-at faults for a small circuit and the patterns that detect them. 2–3 wks4. BIST and boundary scan
MBIST, LBIST (LFSRs, signatures), JTAG (IEEE 1149.1) and IEEE 1500/1687.
MILESTONEBuild an LFSR-based pattern generator and signature register in Verilog. ongoing5. Test-mode timing and interviews
Test-mode STA, shift power and IR drop, coverage reports.
MILESTONEA write-up comparing coverage with and without test points. FPGA engineer
Build hardware you can reprogram, and ship it on real boards.
Suits: People who want to see their design run on hardware quickly. Common in defence, telecom, test equipment and finance.
3–4 wks1. Digital logic and Verilog/VHDL
RTL fundamentals and testbenches.
MILESTONEA tested counter, FSM and UART transmitter. 3–4 wks2. FPGA architecture
LUTs, CLBs, block RAM, DSP slices, clocking resources and I/O.
MILESTONEMap a design by hand and compare with the tool's resource report. 3–4 wks3. Timing closure on FPGA
Constraints, clock domains, pipelining for FPGA fabric.
MILESTONEA design at a clock target that fails at first, then closes after pipelining. 3–4 wks4. Board bring-up and debug
Pin constraints, programming, on-chip logic analysers, and interfacing with sensors and displays.
MILESTONEThe LED-blink tutorial, then a UART to your PC. ongoing5. Systems and interviews
AXI, soft processors, high-level synthesis basics.
MILESTONEAn accelerator (filter, crypto or image operation) running on a dev board. ASIC design engineer (generalist)
Understand the whole flow, and own a block end to end.
Suits: People who want breadth first, before specializing. It's a good fit for smaller companies and design-services roles.
3–4 wks1. Digital logic and RTL
RTL design and verification basics.
MILESTONEA small tested block (FIFO or UART). 3–4 wks2. Synthesis
Constraints, reports and gate-level netlists.
MILESTONESynthesize your block with Yosys and explain the report. 2–3 wks3. DFT basics
Scan and ATPG concepts.
MILESTONEDescribe the DFT plan for your block. 4–5 wks4. Physical design and STA
The PnR flow, timing and sign-off.
MILESTONETake your block through OpenLane to GDS. ongoing5. Interviews
Explain trade-offs across the flow.
MILESTONEA one-page write-up of your block's journey from RTL to GDS. Analog / mixed-signal engineer
Design the circuits that touch the real, continuous world.
Suits: People who love circuit theory and intuition. Usually needs an M.Tech, and the roles are scarce and well paid.
4–6 wks1. Device and circuit fundamentals
MOSFET operation, small-signal models, and single-stage amplifiers.
MILESTONEHand-analyse and simulate a common-source amplifier. 4–6 wks2. Amplifiers and feedback
Differential pairs, current mirrors, op-amps, feedback, stability and compensation.
MILESTONEA two-stage op-amp meeting gain, bandwidth and phase-margin targets. 4–6 wks3. Building blocks
Bandgap references, LDOs, comparators, data converters (ADC/DAC) and PLL basics.
MILESTONEA bandgap reference with a temperature sweep. 3–4 wks4. Layout and variation
Matching, parasitics, corners, Monte Carlo analysis and layout techniques.
MILESTONEThe layout of your op-amp, with post-layout simulation. ongoing5. Interviews
Intuition questions and design trade-offs.
MILESTONEA design report with specs vs results.