Semiconductor interview questions, with worked answers, band diagrams and numericals

The Fermi level E_F is the energy at which a state has a 50% chance of being occupied by an electron. Its position relative to the band edges sets the carrier densities: the closer E_F is to the conduction band, the more electrons; the closer to the valence band, the more holes.

• Intrinsic: E_F sits at E_i, very near mid-gap.
• n-type: E_F moves up toward E_c by kT·ln(N_D/n_i), about 0.36 eV for 10¹⁶ cm⁻³.
• p-type: E_F moves down toward E_v by kT·ln(N_A/n_i).

In equilibrium E_F is the same everywhere in a connected system. That rule is what fixes the shape of band diagrams for junctions and contacts.

In equilibrium, n·p = n_i², independent of doping. Thermal generation creates electron–hole pairs at a rate set by temperature and bandgap, and recombination removes them at a rate proportional to n·p. Equilibrium is where the two balance, which fixes the product.

Adding donors raises n. With more electrons available, holes recombine faster, so p falls until n·p is back to n_i². For silicon doped with 10¹⁶ donors, n ≈ 10¹⁶ and p ≈ 10⁴ cm⁻³: a ratio of a trillion.

• Drift is carrier motion caused by an electric field: J = q(nμ_n + pμ_p)E. It's what flows in a resistor.
• Diffusion is motion from high to low concentration, with no field needed: J_n = qD_n(dn/dx), J_p = −qD_p(dp/dx). It's how minority carriers move through the neutral regions of a diode or the base of a BJT.

The two are linked by the Einstein relation D/μ = kT/q, because both come from the same random thermal motion and scattering. In an equilibrium PN junction, large drift and diffusion currents flow in opposite directions and cancel exactly, which is why no net current flows.

In a direct bandgap material (GaAs, GaN, InP), the conduction-band minimum and valence-band maximum occur at the same crystal momentum. An electron can drop straight down and emit a photon. In an indirect material (Si, Ge), they occur at different momenta, so the transition also needs a phonon to supply the momentum difference.

That three-particle process is far less likely, so in silicon, radiative recombination loses badly to non-radiative paths through defects. Silicon LEDs are very inefficient, which is why LEDs and lasers use III–V materials. Silicon still works well as a photodetector, because absorption only needs the photon energy to exceed the gap, helped by phonons.

Between about 5 and 7 V both mechanisms contribute and the temperature coefficients roughly cancel, which is why reference diodes near 5.6 V are so stable.

Forward bias lowers the junction barrier by qV. The number of majority carriers with enough energy to cross a barrier follows the Boltzmann tail of their energy distribution, so it grows as e^qV/kT. Those carriers are injected as minority carriers and diffuse away, and that diffusion current is the diode current.

I = I_S·(e^(qV/nkT) − 1)
At 300 K, kT/q = 25.9 mV
ln(10) × 25.9 mV ≈ 59.6 mV → 10× current per ~60 mV (n = 1)

With recombination in the depletion region the ideality factor n approaches 2, giving about 120 mV per decade. At high current, series resistance and high-level injection bend the curve further.

For a p-type substrate:

• Accumulation (gate negative): holes pile up at the surface, so the capacitance is just the oxide, C_ox.
• Depletion: holes are pushed away, leaving a growing depletion layer in series with the oxide, so C falls.
• Inversion (gate above V_T): electrons form a layer at the surface.

At low frequency, the inversion electrons can be generated and recombined fast enough to follow the signal, so C returns to C_ox. At high frequency they can't (thermal generation is slow), so only the depletion edge responds and C stays at its minimum. With a fast voltage sweep, even the DC inversion layer can't form and the device goes into deep depletion, with C falling below the minimum.

V_T = V_FB + 2φ_F + Q_dep/C_ox
V_FB = φ_ms − Q_ox/C_ox

• Work-function difference φ_ms between gate and channel: in modern processes, chosen with different work-function metals for NMOS and PMOS.
• Channel doping: raises 2φ_F and the depletion charge, so higher doping means higher V_T. Adjusted with V_T implants, or by fin and sheet doping.
• Oxide capacitance: thinner or higher-k dielectrics shrink the depletion-charge term.
• Fixed oxide charge shifts V_FB.
• Body bias: reverse body bias raises V_T through the body effect.

In short-channel devices, DIBL and V_T roll-off also lower V_T, so the effective value depends on length and drain voltage.

In an NPN transistor, forward-biasing the base–emitter junction injects electrons into the base. They diffuse across and are swept into the collector by the reverse-biased base–collector junction. Current gain depends on two things:

• Emitter efficiency: the B–E current should be mostly electrons going into the base, not holes going back into the emitter. A heavily doped emitter and a lightly doped base make the electron injection dominate.
• Base transport: electrons must cross the base before recombining. A base much thinner than the diffusion length keeps recombination low and also makes the transistor faster.

The limits: too thin or too lightly doped a base gives punch-through and a strong Early effect; too heavy an emitter causes bandgap narrowing that lowers efficiency. That's why HBTs use a wider-gap emitter instead.

A metal on a semiconductor usually forms a Schottky barrier, because Fermi-level pinning by surface states fixes the barrier height largely independent of the metal. Carriers then cross mainly by thermionic emission over the barrier, which rectifies.

To make an ohmic contact, the semiconductor under the metal is heavily doped (around 10²⁰ cm⁻³). The depletion region becomes only a few nanometres thick, so carriers tunnel straight through it in both directions. Contact resistance then depends exponentially on the barrier height divided by √doping. A silicide such as NiSi is used to lower the resistance further.

A Schottky diode is faster than a PN diode because it conducts with majority carriers only, so there's no stored minority charge to remove at turn-off.

In a long transistor the gate alone controls the barrier between source and channel. In a short one, the source and drain depletion regions take up a large part of the channel, so less charge is left for the gate to control.

• V_T roll-off: V_T drops as gate length shrinks, because the junctions "share" the depletion charge.
• DIBL (drain-induced barrier lowering): a high drain voltage reaches through and lowers the source barrier, so V_T drops as V_DS rises. Measured in mV of V_T shift per volt of V_DS.
• In the extreme the depletion regions merge and current flows deep below the surface: punch-through.

Controls: thinner gate dielectric (high-k), shallow source/drain extensions, halo or pocket implants, and, most effectively, multi-gate structures (FinFET, GAA) or fully depleted SOI, where the gate surrounds a thin channel.

Below roughly 25 nm, a planar gate on top of the channel couldn't stop the drain from influencing the deep parts of the channel. Leakage, DIBL and variability rose, and V_DD couldn't keep scaling.

• FinFET: the channel is a thin vertical fin with the gate on three sides. A thin body means no deep path the gate can't reach, so subthreshold swing and DIBL improve sharply, and the channel can be lightly doped, cutting random dopant variation.
• GAA nanosheets: the gate wraps all four sides of stacked horizontal sheets, giving even better control, and the sheet width can be varied for continuous drive strength instead of whole-fin steps.
• Next: CFET, which stacks NMOS on PMOS to shrink cell area further.

The idea throughout is to keep the channel thinner than the gate's "natural length", so the gate stays in charge of the barrier.

Measure reverse current at several temperatures and plot ln(I) against 1/T. The slope gives an activation energy E_a.

• E_a ≈ E_g (about 1.1 eV): diffusion current from the neutral regions, which scales with n_i². The junction is behaving ideally; the issue is design or lifetime.
• E_a ≈ E_g/2 (about 0.55 eV): generation through traps in the depletion region, which scales with n_i. Look for metal contamination, implant damage or a poor anneal.
• Very low E_a and strong field dependence: trap-assisted or band-to-band tunnelling, pointing to very high doping where it shouldn't be.

Then compare diodes of different area and perimeter. Leakage that scales with perimeter points to the edges: isolation, surface states or etch damage.

This is NBTI, negative bias temperature instability. A negative gate bias at high temperature creates interface traps and charges pre-existing traps in the dielectric, so |V_T| rises and drive current falls. When the stress is removed, some of the trapped charge is released, so part of the shift recovers within micro- to milliseconds.

• Measure fast, right after stress. A slow measurement lets recovery hide much of the real shift; this is why two labs can report very different NBTI numbers on the same devices.
• Characterise the shift against time, voltage and temperature to extrapolate to the product lifetime.
• In circuits, design for end-of-life V_T with ageing-aware timing, and avoid holding PMOS devices in constant stress where possible.

• Parallel shift along the voltage axis: fixed charge in the oxide or a different gate work function. Both change V_FB without changing the shape.
• Stretch-out, a less steep transition: interface traps. They change charge state as the surface potential moves, so more gate voltage is needed to sweep through depletion. Quantify with high–low frequency or conductance methods.
• Hysteresis between up and down sweeps: mobile ions (sodium, potassium) moving in the oxide, or slow border traps charging and discharging. A bias-temperature stress test separates them: mobile ions give a large, temperature-activated shift.

Each points to a different process step: clean chemistry for ions, the post-oxidation or forming-gas anneal for interface traps, the oxidation and deposition conditions for fixed charge.

Carriers generated inside the depletion region are swept out quickly by the field. Carriers generated in the neutral regions have to diffuse to the junction first, which can take microseconds. That slow diffusion tail dominates the response, especially for longer wavelengths that are absorbed deep in the silicon, below the depletion region.

• Increase reverse bias to widen the depletion region.
• Use a PIN structure: a thick intrinsic layer makes most absorption happen in the high-field region.
• Make the neutral regions thin, or use a material with stronger absorption at the wavelength.

It comes down to the temperature coefficient of the on-state voltage.

• A power MOSFET's on-resistance rises with temperature, because mobility falls with phonon scattering. If one device runs hotter, its resistance goes up and current shifts to its cooler neighbours. The system is self-balancing.
• A PN junction's forward voltage falls by about 2 mV/°C at constant current. A hotter BJT or diode draws more current, which heats it further: current hogging and possible thermal runaway. Bipolar devices need emitter ballast resistors or careful matching.
• IGBTs sit in between: they have a crossover current above which their coefficient becomes positive, so modern field-stop IGBTs parallel well at rated current.

Not necessarily: this is expected. Oxide breakdown follows weakest-link statistics. A large capacitor is effectively many small ones in parallel, and it fails when its weakest spot fails, so time to breakdown falls with area.

Breakdown times follow a Weibull distribution. On a Weibull plot, data from different areas line up once scaled by area, using the Weibull slope β:

t₂ / t₁ = (A₁ / A₂)^(1/β)

So check whether the large and small structures fall on the same scaled line. If they do, the oxide is behaving normally, and the result is used to project lifetime to the full chip area. If the large structures fall well below the scaled line, or the plot is bimodal, there's an extrinsic defect population (particles, contamination, thinning at edges) that needs fixing.