CMOS interview questions, with worked answers, sizing and numericals

• Cut-off (V_GS < V_T): no inversion channel, so only a small subthreshold current flows, falling about tenfold for every ~60–100 mV below V_T.
• Linear (V_GS > V_T, V_DS < V_GS − V_T): the channel extends from source to drain and the device acts like a voltage-controlled resistor.
• Saturation (V_DS ≥ V_GS − V_T): the channel pinches off near the drain and the current depends mainly on V_GS, rising only slightly with V_DS through channel-length modulation.

linear     : I_D = µC_ox(W/L)·[(V_GS − V_T)·V_DS − V_DS²/2]
saturation : I_D = ½·µC_ox(W/L)·(V_GS − V_T)²·(1 + λ·V_DS)

In short-channel devices, velocity saturation makes the current closer to linear in (V_GS − V_T), which is why the alpha-power model with α between 1 and 1.5 is used for estimates.

As V_in rises from 0 to V_DD, the output stays high (NMOS off), falls steeply around the switching threshold V_M where both devices are saturated and the gain is highest, then settles at 0 (PMOS off).

At either stable input, one transistor is off, so there's no DC path from V_DD to ground. The only static current is leakage. Current flows from supply to ground only briefly while the input passes through the middle region.

Holes have roughly half the mobility of electrons in silicon, so a PMOS of the same size conducts about half the current and has about twice the on-resistance. Making it about twice as wide gives the pull-up and pull-down equal strength, so:

• rise and fall delays are roughly equal, and
• the switching threshold V_M sits near V_DD/2, giving balanced noise margins.

It isn't a fixed rule. The exact ratio depends on the process (strain engineering and FinFETs change hole mobility a lot), and for minimum average delay the best ratio is smaller, about the square root of the mobility ratio, because a wider PMOS also loads the previous stage.

A NAND puts its NMOS in series and its PMOS in parallel. A NOR does the opposite: the slow PMOS go in series. For equal drive to a unit inverter (NMOS 1, PMOS 2):

The NOR is larger, has more input capacitance and is slower for the same drive, and the gap grows quickly with more inputs (NOR3 needs PMOS of width 6). That's why libraries and synthesis favour NAND-based logic.

• Dynamic switching power, αCV²f: usually the largest. Reduce activity with clock gating and operand isolation, reduce capacitance with smaller devices and shorter wires, and above all reduce voltage (DVFS), since it's squared.
• Short-circuit power: both devices conduct briefly during a transition. Keep input edges sharp and matched to output edges.
• Leakage: subthreshold, gate-oxide, junction and GIDL current. Reduce it with high-V_T cells off the critical path, transistor stacking, power gating, body biasing and lower standby voltage.

Leakage rises steeply with temperature and with lower V_T, so in advanced nodes it can be a third or more of total power, and it's the dominant term in standby.

In bulk CMOS, the PMOS source, n-well, p-substrate and NMOS source form a parasitic PNPN structure: a vertical PNP and a lateral NPN connected as a thyristor. If a current injection (an I/O overshoot, an ESD event, a supply glitch) turns one transistor on, its current flows through the well or substrate resistance and turns the other on. If the loop gain exceeds one, the structure latches into a low-resistance path from V_DD to ground, which can only be cleared by removing power and may destroy the chip.

• Place well and substrate taps close to the transistors to keep the parasitic resistances low.
• Use guard rings around I/O and other devices that can inject current.
• Keep NMOS and PMOS apart where rules require, and use epitaxial wafers, deep or retrograde wells, or SOI.

Take the unit inverter as NMOS width 1 and PMOS width 2. The worst-case pull-down and pull-up paths of each gate must match those resistances.

• NAND3: three NMOS in series, each width 3; three PMOS in parallel, each width 2 (only one has to pull up). Input capacitance per input = 3 + 2 = 5, so g = 5/3.
• NOR3: three NMOS in parallel, each width 1; three PMOS in series, each width 6. Input capacitance per input = 1 + 6 = 7, so g = 7/3.

The general results are (n + 2)/3 for an n-input NAND and (2n + 1)/3 for an n-input NOR. The NOR's logical effort grows twice as fast with fan-in, which is the quantitative version of "avoid wide NORs".

For a chain of inverters, path effort F = H = 64. The delay is lowest when every stage has the same effort, and the best effort per stage is about 4.

N = log₄(64) = 3 stages
f = 64^(1/3) = 4 per stage
Sizes: 1 → 4 → 16 (each stage drives 4× its own input)
Delay D = N·f + N·p_inv = 3 × 4 + 3 × 1 = 15 τ

A single inverter driving the load directly would take about 64 + 1 = 65 τ. If the output must not be inverted, compare 2 and 4 stages: 2 stages (f = 8) give 18 τ, 4 stages (f ≈ 2.83) give about 15.3 τ, so 4 is the better even-stage choice.

A dynamic gate has a clocked PMOS that precharges the dynamic node high while the clock is low, and an NMOS network plus a clocked foot transistor that conditionally discharges it while the clock is high. Domino adds a static inverter after the dynamic node, so outputs start low and can only rise during evaluation. That monotonic behaviour lets domino gates drive each other in a chain within one clock phase.

• Charge sharing: internal stack nodes take charge from the dynamic node. Fix it by precharging internal nodes and with a keeper.
• Leakage: the floating high node slowly discharges, giving a minimum operating frequency unless a keeper holds it.
• Noise: a glitch on an input can discharge the node, and it can't recover until the next precharge.
• Only non-inverting functions, so dual-rail logic is needed for full functionality; plus extra clock load and power.

The cell is two cross-coupled inverters (pull-ups PU, pull-downs PD) and two NMOS access transistors (PG) to the bit lines.

• Read stability: during a read, the node storing 0 is connected through the access transistor to a precharged-high bit line, so it rises. PD must win that fight comfortably, so the cell ratio PD/PG is kept above about 1.2–2. Otherwise the bump can flip the cell.
• Writeability: to write, the bit line pulls the node storing 1 down through the access transistor, fighting the PU. PG must beat PU, so the pull-up ratio PU/PG is kept small, with PU usually the weakest device.

So the strength order is PD > PG > PU. At low voltage and with random variation these margins shrink, which is why assists (word-line underdrive, negative bit line) and 8T cells with a separate read port exist.

A wire's resistance and capacitance both grow linearly with length L. Its delay is roughly proportional to R×C, so it grows with L². For a distributed RC line, the Elmore delay is about 0.38·r·c·L², where r and c are per unit length.

Splitting the wire into k segments with a repeater after each one makes each segment's delay proportional to (L/k)², and the total is k times that plus k repeater delays. The wire part falls as L²/k, so for long wires the total grows only linearly with L once the repeater count is optimised.

• Upper metal layers have lower resistance and are used for long routes.
• Too many repeaters cost area, power and their own delay, so there is an optimal spacing set by the technology.

With the gate at V_DD, an NMOS passing a 1 charges its output until V_GS falls to V_T, so the output stops at about V_DD − V_T, made worse by the body effect. Passing a 0, V_GS stays at V_DD and the output reaches 0. A PMOS is the opposite: a strong 1, but a 0 that stops at |V_Tp|.

A transmission gate puts an NMOS and a PMOS in parallel with complementary gate signals, so the pair passes both levels at full swing. It's used in multiplexers, XOR gates, latches and flip-flops.

• A degraded 1 into a static inverter leaves its PMOS slightly on, wasting static current; NMOS-only designs need a level restorer.
• Transmission gates don't add drive, so long chains must be buffered every few stages.

This is a read-stability failure. During a read, the 0 node rises against the pull-down transistor. At low V_DD the read static noise margin shrinks, and random V_T mismatch pushes the weakest cells, far out in the tail of millions, past the point where the bump flips them.

• Check which corner fails. Read stability is usually worst with a strong access transistor and a weak pull-down, as in the FS corner.
• Apply read assist: lower the word-line voltage slightly to weaken the access transistor.
• Raise the array supply relative to logic, or use a separate SRAM rail.
• For low-voltage arrays, use an 8T cell, whose separate read port doesn't disturb the storage nodes.

Suspect charge sharing. Suppose the top transistor of the pull-down stack turns on while the lower ones stay off. The dynamic node, precharged high, now shares its charge with the internal node below, which may have been left at 0 from an earlier evaluation. The node voltage drops to V_DD·C_dyn/(C_dyn + C_int). If that falls below the inverter's switching threshold, the output switches falsely even though the logic says it shouldn't.

It depends on the history of the internal nodes, which is why it appears only for certain sequences.

• Add PMOS transistors that also precharge the internal nodes.
• Use or strengthen the keeper.
• Reorder the stack so the inputs most likely to switch early are nearer ground, and keep internal capacitance small.
• Lower the domino inverter's switching threshold slightly, so a small droop doesn't trip it, at some cost in speed.

• Process corner: these dies may be on the fast side, with lower V_T. Subthreshold leakage changes by about 10× for every 60–100 mV of V_T, so a small shift explains a large factor.
• Temperature: leakage roughly doubles every 10–20 °C. Check the junction temperature during the measurement, not the ambient.
• Estimate assumptions: was the estimate made at the typical corner, at room temperature, or with the wrong mix of high-V_T and low-V_T cells?
• Mechanisms not in the model: gate leakage, GIDL, junction leakage, or power-gated blocks that never actually turn off.
• Design issues: floating inputs causing crowbar current, or contention on a bus.

Measure leakage against temperature and supply voltage. Each mechanism has a different signature, which separates them.

• Wiring capacitance and resistance that the schematic didn't include, including coupling to neighbouring nets.
• Diffusion capacitance: source and drain areas and perimeters are larger than the schematic defaults, especially where diffusion isn't shared.
• Contact and via resistance, plus resistance in thin local interconnect.
• Layout-dependent effects: the distance to the well edge and the length of diffusion change V_T and mobility.
• Folding and finger choices that added gate resistance or capacitance.

Check the extracted netlist node by node against the schematic to find where the capacitance was added, then fix the layout: share diffusion, shorten critical nets, widen or add parallel vias, and move away from well edges where possible.

This is simultaneous switching noise, or ground bounce. When many drivers switch together, the total current changes very quickly through the package and bond-wire inductance, creating V = L·di/dt on the internal supply and ground. Quiet outputs ride on the bounced ground and look like glitches to the receiver, and internal logic sees a temporarily reduced supply.

• Add more power and ground pins and bumps, close to the switching drivers.
• Add on-chip decoupling capacitance.
• Use slew-rate control on output drivers, and stagger switching where the protocol allows.
• Use differential signalling or data-bus inversion to reduce the number of simultaneous transitions.

When the header switches turn on, the block's discharged internal capacitance charges all at once. The resulting rush current pulls the shared supply down, and the always-on neighbour sees a droop deep enough to fail timing or corrupt state.

• Turn the power switches on gradually: a weak "trickle" set first, then the main switches, often daisy-chained so they turn on one after another.
• Add decoupling capacitance and check the supply network's dynamic IR drop for the wake-up event.
• Delay releasing the block's isolation and reset until its supply has settled, usually with an acknowledge signal from the end of the switch chain.