NMOS/PMOS operation, static & dynamic power, and latch-up — the transistor-level questions behind every digital gate.
250+ carefully curated questions with detailed explanations, in one downloadable ebook.
CMOS questions test your grasp of what's happening at the transistor level inside the gates you design with every day — power, noise margins, and the layout considerations that keep a chip reliable.
These come up in both digital and analog-adjacent interviews, since CMOS is the shared foundation underneath both.
How complementary transistors implement logic.
Building gates from pull-up and pull-down networks.
Where power goes in a CMOS circuit.
A failure mode unique to CMOS technology.
How much noise a gate can tolerate before it misbehaves.
Practical transistor sizing decisions.
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