SystemVerilog interview questions, with code answers, output-tracing problems and a real code review

• logic: a 4-state variable. It can be driven by one continuous assignment or from procedural code, but not by multiple drivers.
• wire: a 4-state net. It resolves multiple drivers, so it's what you need for tri-state buses and inout ports.
• bit: a 2-state variable. Faster and smaller in simulation, but an X or Z assigned to it becomes 0.

logic [7:0] a;      // one driver, can hold X
wire  [7:0] bus;    // many drivers, resolved
bit   [7:0] b;

initial begin
  b = dut.data_out; // if data_out is X, b reads 0: the bug is hidden
end

Rule of thumb: use logic (or nets) for anything sampled from the DUT, so X propagation stays visible; use 2-state types for testbench-internal counters and indices.

byte payload[];            // dynamic: size chosen at run time
payload = new[len];

pkt  expected[$];          // queue: push at one end, pop at the other
expected.push_back(p);
p = expected.pop_front();

bit [31:0] mem [bit [31:0]];   // associative: only touched addresses exist
mem[32'h8000_0000] = 32'hDEAD_BEEF;
if (mem.exists(addr)) rdata = mem[addr];

• Dynamic array when the size is decided once (a randomised payload length).
• Queue when items are added and removed over time, especially in order (a scoreboard's expected list).
• Associative array when the index space is huge or sparse (a memory model, or lookup by transaction ID).

fork
  drive_stimulus();
  wait_for_timeout(1000);
join_any                 // continue when either finishes
disable fork;            // kill whichever is still running

fork
  monitor_bus();         // keep running in the background
join_none                // parent continues immediately
...
wait fork;               // later: block until all children finish

• join waits for every child.
• join_any waits for the first child; the others keep running.
• join_none waits for nothing; children start when the parent next blocks.

disable fork kills all child threads of the current process, including ones forked earlier, so wrap the fork in its own begin...end isolation thread if other children must survive.

Interfaces are static, elaborated in the module hierarchy; classes are dynamic, created at run time. A class can't contain an interface instance, but it can hold a handle to one: that's a virtual interface.

interface bus_if (input logic clk);
  logic       valid;
  logic [7:0] data;
endinterface

class driver;
  virtual bus_if vif;            // set from the top before run
  task drive(byte d);
    @(posedge vif.clk);
    vif.valid <= 1'b1;
    vif.data  <= d;
  endtask
endclass

// top module:  drv.vif = bus0;   (in UVM: uvm_config_db#(virtual bus_if)::set)

It also makes the driver reusable: the same class can drive any instance of bus_if.

class hdr; int id; endclass
class pkt;
  int  len;
  hdr  h = new();
  function pkt deep_copy();
    deep_copy   = new();
    deep_copy.len  = len;
    deep_copy.h.id = h.id;       // copy the contents, not the handle
  endfunction
endclass

pkt a = new(), b, c, d;
b = a;              // same object: changing b.len changes a.len
c = new a;          // shallow: new pkt, but c.h and a.h are the same hdr
d = a.deep_copy();  // fully independent

In a scoreboard this matters: if the monitor reuses one object and the scoreboard stores the handle, every stored entry changes when the monitor writes the next transaction. Store a copy.

• always_comb runs once at time 0 (so outputs aren't stuck at X until an input changes), is sensitive to signals read inside called functions, forbids other processes writing its outputs, and lets tools warn when it would infer a latch.
• always_ff states the intent "flip-flops"; tools flag anything that isn't a single clocked event control.
• always_latch documents an intentional latch.

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) q <= '0;
  else        q <= d;

always_comb begin
  y = b;                 // default first: no latch
  if (sel) y = a;
end

class base_pkt;
  virtual function void show();  $display("base");  endfunction
endclass

class err_pkt extends base_pkt;
  function void show();  $display("error packet");  endfunction
endclass

base_pkt b;
err_pkt  e = new();
b = e;        // base handle, derived object
b.show();     // prints "error packet"
              // without 'virtual' in base_pkt, prints "base"

With virtual, the call is chosen at run time by the object's type; without it, at compile time by the handle's type. Polymorphism is what lets a driver handle a queue of base handles that actually point to many packet types, and what makes UVM factory overrides work.

class pkt;
  rand bit [31:0] addr;
  rand bit [7:0]  len;
  rand bit        err;

  constraint c_len  { len inside {[1:64]}; }
  constraint c_addr { addr inside {[32'h1000 : 32'h1FFF]};
                      addr[1:0] == 2'b00; }
  constraint c_err  { err dist { 1 := 1, 0 := 9 }; }
endclass

pkt p = new();
if (!p.randomize() with { len == 64; })       // corner case for one test
  $fatal(1, "randomize failed");
p.c_err.constraint_mode(0);                   // turn one constraint off

Then mention the tools for later tests: soft for defaults a test may override, solve...before when you need a skewed distribution, and always checking the return value of randomize().

typedef enum {RD, WR, RMW, NOP} cmd_e;

covergroup pkt_cg with function sample(bit [7:0] len, cmd_e cmd);
  cp_len : coverpoint len {
    bins small = {[1:8]};
    bins mid   = {[9:32]};
    bins large = {[33:64]};
    illegal_bins zero = {0};
  }
  cp_cmd : coverpoint cmd;               // one bin per enum value
  x_len_cmd : cross cp_len, cp_cmd {
    ignore_bins no_nop = binsof(cp_cmd) intersect {NOP};
  }
endgroup

pkt_cg cg = new();
// in the monitor, once per observed packet:
cg.sample(p.len, p.cmd);

Explain the choices: explicit bins instead of 256 auto bins, an illegal bin for a value the spec forbids, and an ignored cross for a combination that can't happen. That's 3 × 4 − 3 = 9 cross bins.

property p_req_ack;
  @(posedge clk) disable iff (!rst_n)
    $rose(req) |-> ##[1:3] ack;
endproperty

a_req_ack : assert property (p_req_ack)
  else $error("ack not seen within 3 cycles of req");
c_req_ack : cover  property (p_req_ack);

• |-> starts checking in the same cycle as the trigger; |=> would start one cycle later.
• $rose(req) avoids starting a new attempt every cycle that req stays high.
• disable iff stops false failures during reset.
• The cover proves the check ever fired; without it, an assertion that never triggers looks the same as one that always passes.

interface bus_if (input logic clk);
  logic valid, ready;
  logic [7:0] data;
  clocking cb @(posedge clk);
    default input #1step output #1;
    input  ready;
    output valid, data;
  endclocking
endinterface

// driver
@(vif.cb);
vif.cb.valid <= 1'b1;        // driven 1 time unit after the edge
if (vif.cb.ready) ...         // value sampled just before the edge

Inputs are sampled in the Preponed region, before anything changes at that edge, so the testbench always sees the value the DUT's flops saw. Outputs are driven a skew after the edge, so the DUT never sees a testbench change in the same delta it samples. Both sides stop depending on simulator ordering.

mailbox #(pkt) gen2drv = new(4);   // bounded: put() blocks at 4 items

// generator thread                   // driver thread
repeat (n) begin                      forever begin
  p = new();                            gen2drv.get(p);  // blocks if empty
  void'(p.randomize());                 drive(p);
  gen2drv.put(p);                     end
end

semaphore bus_key = new(1);           // one owner of a shared bus
bus_key.get(1);  do_transfer();  bus_key.put(1);

• Mailbox: passing items between threads, with built-in blocking. Bounded mailboxes give back-pressure.
• Queue: storage inside one thread or class; it never blocks, so a consumer must poll or use events.
• Semaphore: mutual exclusion on a shared resource, not data transfer.

1. Check what that test adds: inline with constraints, a factory override with extra constraints, or state variables (non-rand fields) set to unusual values before the call.
2. Read the solver report: most simulators print the conflicting constraints when randomisation fails; turn on verbose constraint debug.
3. Bisect: switch constraints off one at a time with constraint_mode(0) until it solves.
4. Check types and widths: a signed field, a too-narrow variable, or an implicit truncation can make a range impossible.
5. Make it loud: if (!obj.randomize()) `uvm_fatal(...) everywhere, so a failure stops the test instead of reusing old values.

• List the holes: which bins or cross bins are empty, and do they share a pattern?
• Can they be hit at all? Some combinations are impossible by design: move them to ignore_bins after checking with the designer, or illegal_bins if hitting them is a bug.
• Are they reachable but unlikely? Read the constraints: a narrow range inside a wide random field may almost never be generated. Add a weighted dist, a dedicated sequence, or a directed test.
• Is the sampling wrong? A covergroup sampled at the wrong time, or not at all in some mode, shows as a hole that no stimulus can fill.

1. Look at attempt and vacuous-pass counts: if the antecedent never matched, every pass is vacuous.
2. Add a cover property on the antecedent and the full property, and check it's hit in regressions.
3. Check the clock and reset: a wrong clock, or disable iff with the wrong polarity, disables the check permanently.
4. Check binding: a bind to the wrong module or to an internal signal renamed by synthesis can leave the assertion unconnected.
5. Break it on purpose: inject a bug or force a signal once, and confirm the assertion fires.

• Blocking calls with no partner: a mailbox.get() or semaphore.get() waiting for something that will never come.
• Events missed: @ev waits for the next trigger; if it fired earlier in the same time step, use wait(ev.triggered).
• Forever threads: forever loops started with join instead of join_none, or never killed.
• UVM objections: a component raised an objection and never dropped it; turn on objection tracing.
• Waiting on the DUT: a handshake that never completes because the DUT is stuck; add a watchdog timeout that reports what it was waiting for.

1. Find the handle from the line number in the error, and the time it happened.
2. Was new() ever called? Declaring a handle doesn't create an object; arrays of handles need each element constructed.
3. Was it constructed too late? Something used it in an earlier phase or at time 0 before the constructor ran.
4. Was it overwritten? A later assignment of null, or a failed $cast used as a task (which errors) vs a function (which returns 0 and leaves the target unchanged).
5. Virtual interfaces: a vif never set from the top or the config DB gives the same error at the first access.

• Races: the testbench and DUT read and write the same signal at the same edge without a clocking block or non-blocking assignments, so the result depends on process order, which the LRM leaves to the tool.
• Unspecified behaviour: the order of fork children, foreach on associative arrays with unusual keys, or uninitialised variables used before assignment.
• Random stability: the same seed doesn't produce the same values across tools.
• Language support: a construct one tool accepts as an extension that another treats differently; lint helps.

Fix the races first: drive and sample through clocking blocks, use <= for anything that crosses an edge, and remove time-0 ordering assumptions.