What do physical design interviews focus on?

The flow from netlist to GDS and the reasoning behind each step: floorplanning, power planning, placement, CTS, routing, setup and hold closure, crosstalk, IR drop, DRC and LVS. Experienced candidates get debugging scenarios, ECO decisions and signoff questions.

How much STA does a PD engineer need?

A lot. Expect to read a timing report, explain setup and hold with clock skew, fix violations at different stages, and talk about MCMM, OCV and CPPR. Many PD interviews spend half their time on timing.

Do I need hands-on tool experience?

It helps a lot, but interviews test concepts and reasoning more than commands. Running a small design through an open-source flow such as OpenROAD with a public PDK is a good way to get real reports to talk about.

Is scripting asked in PD interviews?

Often. Tcl is used to drive the tools and Python or Perl to parse reports. Freshers may be asked to write a small loop or report filter; experienced engineers are asked how they automated parts of their flow.

What should a fresher prepare first?

The flow and its inputs (netlist, LEF, Liberty, SDC), floorplanning and power planning, placement and congestion, CTS goals, routing, and setup and hold with clock skew. Then IR drop, crosstalk, DRC and LVS.

How is PD different from STA as a role?

PD engineers implement the layout and fix problems physically: placement, clock trees, routing, power grids and ECOs. STA engineers own constraints and timing signoff across modes and corners. The two work closely, so each interview covers the other's basics.

Physical Design Interview Questions: 90+ with Answers

Physical design interviews check whether you can take a synthesised netlist to a clean, manufacturable layout, and whether you understand why each step exists. Definitions get you through the opening minutes; after that it's "this region is congested, what do you check?" and "hold broke after CTS, why?"

The best answers place every problem on the flow: which stage introduces it, which report shows it, and what a fix costs elsewhere. Start with the formula sheet and calculator, skim the 50 questions by topic, then work through the worked answers, numericals and the QoR report before opening each answer.

HOW IT'S ASKED

Three levels of a physical design interview

LEVEL 1

Flow & inputs

The PD flow end to end, what LEF, Liberty, SDC and the netlist each provide, utilisation, macro placement, power rings and straps, and what CTS and routing produce.

LEVEL 2

Closure & trade-offs

Setup and hold fixing at each stage, skew and latency, congestion versus timing, crosstalk, IR drop, MCMM and OCV, and what each fix costs in area, power or routability.

LEVEL 3

Debugging & signoff

"Timing was clean after placement and fails after route", DRC explosions, IR hotspots, LVS mismatches, late ECOs and tapeout readiness. They're testing method, not memory.

HOW TO ANSWER

Six habits of strong PD answers

Place it on the flow

Floorplan, place, CTS, route, signoff. Say which stage introduces the problem and which stage should fix it; that alone answers half the "why" questions.

Name the report

Congestion map, timing report, CTS skew summary, IR map, DRC database. Interviewers trust answers that start from evidence, not guesses.

Fix root causes, not symptoms

A thousand transition violations after routing usually have one cause: a congested region, a weak driver or a bad floorplan. Find the cluster first.

Every fix has a cost

Upsizing hurts power and area, hold buffers hurt congestion, spreading cells hurts wirelength. Name what you'd give up before you're asked.

Say which corner

Setup at slow, hot and low voltage, hold at fast and cold, leakage at fast and hot. A violation without its scenario is half a diagnosis.

Tell one real story

"Tell me about a closure problem you solved" is almost guaranteed. Prepare one: the symptom, the report, the root cause, the fix and the result.

FORMULA SHEET

The PD numbers interviewers expect you to work out

Most physical design numericals use one of these relationships.

UTILISATIONutil = standard-cell area / (core area − macro and blockage area)Typical starting targets are 60–75%; higher saves area but leaves less room to route and optimise.

CORE SIZEcore area = macro area + cell area / util · W = √(area / AR), H = AR·W

SETUP SLACK(T + L_capture − t_su − uncertainty) − (L_launch + t_cq + t_data)

HOLD SLACK(L_launch + t_cq + t_data,min) − (L_capture + t_h + uncertainty)The clock period doesn't appear, so a slower clock never fixes hold.

SKEWskew = L_capture − L_launch · positive skew helps setup, hurts hold

OCV & CPPRlate paths × late derate, early paths × early derate · CPPR credit = common clock delay × (late − early derate)

IR DROPΔV = I · R_grid, I ≈ P / V_DD · budget often ~5% of V_DD (static plus dynamic)

EMwidth ≥ I_avg / J_max (current per µm of width for that layer and temperature)

WIRE DELAYdistributed RC ≈ 0.38·r·c·L² · repeaters make it roughly linear in L

CROSSTALKcoupling noise ≈ ΔV_aggr·C_c / (C_c + C_g) · Miller factor 0–2 on C_c for delta delay

ANTENNAratio = metal area connected to the gate during etch / gate area ≤ rule limit

POWERP_dyn = α·C·V²·f · clock network often 30–50% of dynamic power

TRY IT

Floorplan & IR-drop estimator

Size the core from cell and macro area, then estimate first-order IR drop from block power and grid resistance.

STD-CELL AREA (mm²)

MACRO AREA (mm²)

TARGET UTILISATION (%)

ASPECT RATIO (H/W)

BLOCK POWER (mW)

V_DD (V)

GRID RESISTANCE (mΩ)

CORE AREA–

CORE W × H–

SUPPLY CURRENT–

IR DROP–

SIGNOFF CHECKS

Which check catches which problem

"What's the difference between DRC and LVS?" is the opener. Knowing what every signoff check compares, and what it can't see, answers the follow-ups.

CHECK	COMPARES	CATCHES	CAN'T SEE
DRC	Layout geometry vs foundry rules	Spacing, width, enclosure, density, via rules	Whether the circuit is the right one
LVS	Layout-extracted netlist vs schematic or netlist	Shorts, opens, missing or extra devices, wrong connections	Timing, IR drop, manufacturability
Antenna	Metal area on gates during each etch step vs ratio limits	Gate-oxide damage risk during manufacturing	Anything after the chip is complete
STA (signoff)	Extracted timing across modes and corners vs constraints	Setup, hold, transition, capacitance, SI delay	Functional bugs, wrong constraints
IR / EM	Voltage and current density across the power grid and signal nets	Static and dynamic droop, wear-out risk	Logic errors; timing unless IR-aware STA is run
Logic equivalence	Final netlist vs earlier netlist or RTL	Function changed by optimisation or ECOs	Timing and physical problems

BROWSE BY TOPIC

50 physical design interview questions across 10 topics

A sample of what PD interviewers ask most. The 616-question ebook covers each topic in much more depth, with every question answered and explained.

Flow & Inputs

What PD starts from, and what it delivers.

What does the PD team receive from synthesis, and what does it hand off at tapeout?
What information does a LEF file carry that the netlist doesn't?
Why does PD need Liberty files at several corners?
What is a sanity check before floorplanning, and what does it catch?
Why can a bad handoff look like an implementation bug?

Floorplanning

Decisions that every later stage lives with.

How do you choose core utilisation and aspect ratio?
What guides macro placement, and why are macros placed first?
What are halos, keep-outs and placement blockages for?
How do you decide where I/O pins go on a block?
Why can a floorplan decision only show its damage after routing?

Power Planning

Getting current to every cell.

What are power rings, straps and follow-pin rails?
How do you decide strap width, pitch and layer?
Why do macros need their own power connections?
What is the difference between static and dynamic IR drop?
How do decap cells help, and what do they cost?

Placement & Congestion

Where cells go, and whether they can be routed.

What happens in global placement versus legalisation and detailed placement?
What causes routing congestion, and how do you see it early?
How do cell padding and density screens reduce congestion?
What is timing-driven placement?
Why can fixing congestion make timing worse?

Clock Tree Synthesis

Delivering the clock with control.

What are the main goals and constraints of CTS?
What is the difference between clock latency and skew?
What is useful skew, and when is it used?
Why do clock nets use non-default routing rules?
H-tree, mesh or multi-source CTS: what are the trade-offs?

Routing

Turning connections into metal.

What do global routing, track assignment and detailed routing each do?
Why does timing change after routing?
What are pin-access problems, and why are they worse at advanced nodes?
What is a routing detour, and how does it hurt timing?
How do you choose layers for critical nets?

Setup & Hold Closure

The centre of most PD interviews.

How do you fix setup violations at placement, after CTS and after routing?
Why do hold violations usually appear after CTS?
How do you fix hold without breaking setup?
What are MCMM scenarios, and why are they needed?
What are OCV derates and CPPR?

Signal & Power Integrity

Second-order effects that break real chips.

What is crosstalk delta delay, and how does it affect setup and hold?
What is a crosstalk glitch, and when is it dangerous?
How do shielding, spacing and layer changes reduce coupling?
How do you fix an IR-drop hotspot?
What causes electromigration, and how is it fixed?

Physical Verification & DFM

Proving the layout is correct and buildable.

What is the difference between DRC and LVS?
How do you debug an LVS short between two nets?
What is the antenna effect, and how is it fixed?
Why do foundries require metal fill and density rules?
What are double-patterning or coloring rules?

ECO, Low Power & Signoff

The last mile to tapeout.

What is a metal-only ECO, and why is it valuable?
How do you prioritise fixes when time is short?
How do power switches, isolation and level shifters affect the floorplan?
What is hierarchical PD, and what are its interface challenges?
What must be clean before you'd sign off for tapeout?

WORKED ANSWERS

18 PD questions, answered the way interviewers expect

Answer out loud first, then open each one. Every answer shows what a strong reply covers, what the interviewer is listening for, and the slip that costs candidates most often.

01Walk me through the physical design flow, with the inputs and outputs.Foundational

Inputs: the synthesised gate-level netlist, constraints (SDC), Liberty timing libraries at each corner, LEF for cell and macro abstracts, the technology file and rule decks, and the power intent (UPF) for low-power designs.

Import and sanity checks: netlist, libraries and constraints load cleanly and agree.
Floorplan: core size, macro placement, I/O pins, blockages.
Power planning: rings, straps, rails and macro hookups.
Placement: global, legalisation, detailed, with timing and congestion optimisation.
CTS: build and balance the clock tree, then fix hold.
Routing: global, track assignment, detailed, then post-route optimisation.
Signoff: extraction, STA across corners, IR/EM, DRC, LVS, antenna, equivalence.

Outputs: the GDSII or OASIS layout, the final netlist, extracted parasitics (SPEF) and signoff reports.

Interviewers listen forThe inputs named precisely, and signoff as more than "run DRC".

Common mistakeLeaving out power planning, or putting CTS after routing.

02What do you consider when placing macros in a floorplan?Foundational

Connectivity and data flow: put macros near the logic and I/O they talk to, and keep heavily connected macros close together.
Edges and channels: macros usually go toward the core boundary so standard cells get a large, continuous region. Leave enough channel width between macros for routing and buffering.
Pin side and orientation: face macro pins toward the logic they connect to, not toward another macro or the die edge.
Halos and blockages: keep cells away from macro edges to protect pin access and avoid congestion in narrow gaps.
Power: macros need strong power connections, and memories can create IR hotspots.

Macro placement is done first because macros are large and fixed; once they're placed, everything else has to work around them.

Interviewers listen forData flow, channels and pin orientation.

Common mistakePacking macros tightly in the centre to "save area".

03Explain power rings, straps and rails. How do you size a power grid?Foundational

Rings run around the core or around macros on wide upper metal, collecting current from the pads or bumps.
Straps (stripes) cross the core in a mesh on upper layers, distributing current evenly.
Rails (follow pins) run along each standard-cell row on the lowest metal, connecting to every cell's VDD and VSS pins, and are stitched up to the straps with via stacks.

Sizing is a trade-off. Wider and denser straps cut IR drop and EM risk but take routing tracks away from signals. Teams start from estimated power, the IR budget (often around 5% of V_DD) and the EM limits for each layer, then refine with IR analysis after placement and again at signoff.

Interviewers listen forThe routing-resource trade-off, not just the structure.

Common mistakeForgetting via stacks, which are often the real bottleneck.

04What is the difference between global placement, legalisation and detailed placement?Foundational

Global placement finds rough positions that minimise wirelength and respect density, treating cells as if they could overlap.
Legalisation snaps every cell onto a legal site in a row with no overlaps, moving it as little as possible.
Detailed placement makes local improvements: swapping, flipping or shifting neighbouring cells to reduce wirelength or fix timing.

Throughout, the tool also optimises: buffering long nets, resizing cells and restructuring logic on critical paths. Congestion is estimated from a quick global route so placement can spread cells where routing demand is too high.

Interviewers listen forThat global placement allows overlap, and why legalisation exists.

Common mistakeDescribing placement as a single step.

05What are the goals of clock tree synthesis?Foundational

CTS builds a buffered network that delivers the clock from its source to every sink, flip-flops, latches and macro clock pins, while meeting:

Skew targets: arrival times at related sinks within a limit.
Latency (insertion delay) targets: not too long, because long trees see more variation.
Transition limits: sharp clock edges at every sink.
Power and area: clock nets switch every cycle, so fewer buffers and shorter wires matter.

Clock nets are usually routed with non-default rules (wider, double-spaced, sometimes shielded) to reduce resistance, crosstalk and EM risk. After CTS, real clock arrival times replace ideal ones, so hold fixing starts here.

Interviewers listen forSkew, latency and transition together, plus clock power.

Common mistakeSaying the goal is "zero skew". Low skew matters, but useful skew is sometimes introduced deliberately.

06What is the difference between global and detailed routing?Foundational

Global routing divides the chip into tiles (g-cells) and assigns each net a path through them, balancing demand against capacity. Its overflow map is the congestion picture.
Track assignment places wire segments onto specific tracks within each tile.
Detailed routing creates the actual metal shapes and vias, connects to pins and fixes design-rule violations.

After routing, real parasitics are extracted, so timing usually changes: detours, coupling capacitance and via resistance appear. Post-route optimisation and SI-aware timing follow.

Interviewers listen forThat global routing predicts congestion and detailed routing creates legal geometry.

Common mistakeAssuming a clean global route guarantees a clean detailed route.

07How do you fix setup violations, and how does the approach change through the flow?Applied

First diagnose: is it data-path delay, clock skew, a high-transition net, a bad constraint, or SI? Then fix in order of least disruption:

Placement: cell resizing, buffering, logic restructuring, moving cells closer, timing-driven placement, and floorplan changes if the path crosses the block.
After CTS: the same plus useful skew, delaying the capture clock or advancing the launch clock where neighbouring paths have slack.
After routing: upsizing, lower-V_T cells (watch leakage), rerouting on faster layers, non-default rules, and fixing crosstalk-induced delay.
Late ECO: small, targeted changes using spare cells or metal-only edits.

Always recheck hold, transition and congestion after each fix, and check across every relevant scenario.

Interviewers listen forDiagnosis before fixing, and stage-appropriate fixes.

Common mistake"Upsize everything", which burns power and can create new violations.

08Why do hold violations appear after CTS, and how are they fixed?Applied

Before CTS, clocks are ideal: every flop sees the edge at the same time, so hold is easy to meet. After CTS, real clock latencies differ. Where the capture flop's clock arrives later than the launch flop's, a short data path can change the captured value before the hold window closes.

Insert delay cells or buffers on the short data path, ideally near the capture flop.
Reduce harmful skew by adjusting the clock tree.
Use slower or higher-V_T cells on the short path.

Hold is fixed at the fast corner, but each delay cell adds to the same path's setup at the slow corner, so check the setup margin first. In a congested region, hundreds of hold buffers can also hurt routability.

Interviewers listen forIdeal versus propagated clocks, and the setup trade-off.

Common mistakeFixing hold before setup is stable, then having to undo it.

09What are MCMM, OCV and CPPR, and why do they matter?Applied

MCMM (multi-corner multi-mode): a chip must work in several functional and test modes, each at several PVT corners. Each mode–corner pair is a scenario, and optimisation must close all of them at once, because a fix in one can break another.
OCV (on-chip variation): even within one die, cells and wires vary. STA applies late derates to paths that should be slow and early derates to paths that should be fast, adding pessimism. Advanced flows use statistical (AOCV, POCV/LVF) derates by depth and distance.
CPPR (clock path pessimism removal): the launch and capture clocks often share a common section of the tree. That section can't be both fast and slow at once, so STA credits back the difference applied to it.

Interviewers listen forWhy CPPR exists, explained with the common-path argument.

Common mistakeTreating OCV as the same thing as corners.

10What is crosstalk, and how does it affect timing?Applied

Neighbouring wires are coupled by capacitance. When an aggressor switches, it injects charge into the victim.

Delta delay: if aggressor and victim switch in opposite directions, the victim slows down (hurting setup); in the same direction, it speeds up (hurting hold). STA must consider the timing windows of both.
Glitch (noise): on a quiet victim, a switching aggressor can create a bump. If it's large enough and reaches a clock, reset or latch, it can cause a functional failure.

Fixes: increase spacing, add shielding (grounded wires between), route on a different layer, upsize the victim driver, reduce aggressor slew, or break long parallel runs. Clock nets often get shielding by default.

Interviewers listen forBoth effects, and which direction hurts setup versus hold.

Common mistakeOnly mentioning noise, not the timing impact.

11What is the difference between static and dynamic IR drop? How do you fix each?Applied

Static IR drop uses average current. It shows whether the grid is strong enough overall and is mostly fixed with wider or denser straps, more vias and more power bumps or pads.
Dynamic IR drop uses switching current over time, so it shows local droops when many cells switch together, for example under a clock edge or in a busy datapath. It's fixed with decap cells near the hotspot, by spreading high-activity cells, staggering clock arrival, and strengthening the local grid.

IR drop matters for timing because cells see a lower supply and slow down. Signoff runs IR-aware STA or adds a voltage margin to account for it.

Interviewers listen forDecaps for dynamic, grid strength for static, and the timing impact.

Common mistakeFixing a dynamic hotspot only by widening straps far away from it.

12What is the antenna effect, and how is it fixed?Applied

During plasma etch, exposed metal collects charge. If that metal connects only to a transistor gate at that point in manufacturing, with no diffusion yet connected to drain it, the charge can stress and damage the thin gate oxide. Foundries limit the ratio of connected metal area to gate area for each layer.

Layer jumping: break the long wire and jump up to a higher metal, so the lower segment connected to the gate is short at the critical etch step.
Antenna diodes: connect a reverse-biased diode to the net to give the charge a safe path, at a small area and capacitance cost.
Route the net so it reaches a driving diffusion earlier, or insert a buffer near the gate.

Interviewers listen forThat it's a manufacturing effect, and why jumping up a layer works.

Common mistakeThinking it's an electrical problem in the finished chip.

13One region of a block is badly congested; the rest is fine. How do you debug it?Scenario / debug

Look at the region on the congestion map: is it horizontal or vertical overflow, and on which layers?
See what's there: high cell density, high-pin-count cells (multiplexers, wide AND-OR cells), a narrow channel between macros, macro pins on the wrong side, or a crowd of hold buffers.
Check the floorplan: are macros forcing nets through a gap? Are I/O pins on the far side from the logic that uses them?
Apply targeted fixes: cell padding or density screens in that region, partial placement blockages, moving or flipping a macro, widening a channel, restructuring high-fan-in logic, or changing pin placement.
Recheck timing, because spreading cells adds wirelength.

Interviewers listen forFinding the cause in the region, not adjusting global settings.

Common mistakeLowering overall utilisation, which wastes area everywhere to fix one spot.

14Timing was clean after placement but fails badly after routing. What happened?Scenario / debug

Estimated versus real wires: placement estimates wire length and RC. After routing, detours around congested areas make nets longer.
Coupling capacitance and crosstalk only appear with real neighbours.
Via resistance and layer choice: critical nets may have been routed on thin, resistive lower layers.
Clock changes: the clock tree's real routing changed latency and skew from post-CTS estimates.
Correlation: the implementation tool's estimates may not match the signoff extractor and STA.

Compare the failing paths' placement and route timing net by net to find where delay was added. Fix the root cause (congestion, layer assignment, NDRs) and improve correlation settings for the next run.

Interviewers listen forDetours, coupling and correlation.

Common mistakeOver-fixing with upsizing instead of finding the detour.

15After CTS, there are thousands of hold violations. What do you check before inserting buffers?Scenario / debug

Constraints: missing false paths or multicycle paths between asynchronous or slow clocks can create thousands of fake violations at once.
Clock definitions: generated clocks, clock groups and uncertainty values all set correctly for post-CTS (propagated) analysis?
Skew pattern: if the violations cluster between two branches of the tree, fix the skew there instead of padding every path.
Scan paths: shift-mode flop-to-flop paths are short and often dominate hold counts; they need the right mode and corner.
Real setup margin: only then insert delay cells, preferably near the capture flops and away from congested regions.

Interviewers listen forChecking constraints and skew before adding thousands of cells.

Common mistakeBlindly running hold fixing, adding area, power and congestion.

16LVS reports a short between VDD and a signal net. How do you find it?Scenario / debug

Use the LVS tool's short-path tracing to find the shortest geometric path between the two nets; it usually points straight at the overlap.
Check recent changes: an ECO, a manual edit, a new filler or a macro abstract that doesn't match its real layout.
Look for overlapping shapes on the same layer, a misplaced via, or a power strap routed over a pin.
Check text labels and pin definitions: a label in the wrong place can merge nets logically even when the geometry is fine.
Fix, rerun LVS on the area, and rerun DRC because the fix itself can create spacing violations.

Interviewers listen forShort tracing and checking abstracts and labels.

Common mistakeReading through thousands of LVS errors from the top; one short often causes most of them.

17Detailed routing finished with thousands of DRC violations. Where do you start?Scenario / debug

Group by type and location. Shorts clustered in one area mean congestion; violations spread evenly suggest a setup problem such as a wrong rule deck, technology file or via definitions.
Check pin access: errors at cell pins point to dense cells or library pins that are hard to reach at that node.
Check around macros and the power grid: blocked tracks and straps that leave too few routing resources.
Fix the cause upstream: reduce local density, add routing blockages or channels, adjust the power grid, then reroute, rather than fixing violations one by one.

Interviewers listen forClassify first: congestion, pin access or setup.

Common mistakeTrying to hand-fix thousands of violations.

18Two days before tapeout, a single setup violation appears in one corner. What do you do?Scenario / debug

Confirm it's real: the right constraints, the right corner, the right parasitics, and agreement between implementation and signoff tools.
Understand why only that corner: a temperature-inversion corner, a different derate, crosstalk only in that scenario.
Choose the smallest safe fix: a cell swap to a lower-V_T or larger variant in place, a small reroute, or a metal-only ECO using spare cells.
Rerun everything affected: all timing scenarios, DRC, LVS, antenna, IR/EM and equivalence, since a late change can break something else.
If the margin is tiny and the path is well understood, discuss a documented waiver with the team rather than taking a risky change.

Interviewers listen forRisk management and full re-verification.

Common mistakeMaking a large change late without rerunning all signoff checks.

SOLVED NUMERICALS

8 PD numericals, solved step by step

These come up in written tests and as quick checks during interviews. Solve each on paper, then tap to check.

N1 · CORE SIZEBEGINNERStandard cells need 1.2 mm², macros take 0.6 mm², and target utilisation is 70%. Find the core area and the side of a square core.Show solution ↓

Cell region = 1.2 / 0.70 ≈ 1.714 mm²
Core area   = 0.6 + 1.714 ≈ 2.31 mm²
Square side = √2.31 ≈ 1.52 mm

Note: add room for macro halos, channels and the power ring on top of this.

N2 · UTILISATIONBEGINNERA 2.0 mm² core contains 0.5 mm² of macros and 1.05 mm² of standard cells. What is the utilisation?Show solution ↓

Available = 2.0 − 0.5 = 1.5 mm²
util = 1.05 / 1.5 = 70%

Note: remember to subtract macros and hard blockages. Dividing by the whole core gives a misleading 52.5%.

N3 · IR DROPBEGINNERA block consumes 400 mW at 0.8 V. Its grid has an effective resistance of 40 mΩ to the worst point. Estimate the IR drop.Show solution ↓

I  = P / V = 0.4 / 0.8 = 0.5 A
ΔV = 0.5 × 0.040 = 20 mV = 2.5% of VDD

Note: a first-order static estimate. Dynamic IR at a busy hotspot is usually much higher.

N4 · SETUP SLACKINTERMEDIATET = 1.0 ns, launch latency 300 ps, capture latency 340 ps, t_cq 60 ps, data path 780 ps, setup 40 ps, uncertainty 50 ps. Find setup slack.Show solution ↓

Arrival  = 300 + 60 + 780          = 1140 ps
Required = 1000 + 340 − 40 − 50   = 1250 ps
Slack    = 1250 − 1140            = +110 ps

Note: the 40 ps of positive skew (capture later) helps setup here.

N5 · HOLD SLACKINTERMEDIATESame clocks (launch 300 ps, capture 340 ps), t_cq 60 ps, shortest data path 40 ps, hold 30 ps, hold uncertainty 20 ps. Is hold met?Show solution ↓

Arrival  = 300 + 60 + 40 = 400 ps
Required = 340 + 30 + 20 = 390 ps
Slack    = 400 − 390     = +10 ps (just met)

Note: the same 40 ps of skew that helped setup eats into hold.

N6 · OCV & CPPRINTERMEDIATELaunch clock path 0.9 ns, data path 1.2 ns, capture clock path 0.9 ns, of which 0.6 ns is common to both clocks. Late derate 1.05, early derate 0.95. How much pessimism does OCV add, and how much does CPPR credit back?Show solution ↓

Launch clock late : 0.9 × 0.05 = +45 ps
Data path late    : 1.2 × 0.05 = +60 ps
Capture clock early: 0.9 × 0.05 = −45 ps (worse for setup)
Total added       = 150 ps
CPPR credit = 0.6 ns × (1.05 − 0.95) = 60 ps
Net pessimism = 150 − 60 = 90 ps

Note: the common 0.6 ns can't be slow and fast at once, which is the whole reason CPPR exists.

N7 · ELECTROMIGRATIONBEGINNERA power strap carries 2.4 mA average. The EM limit on its layer is 1.2 mA per µm of width. What width is needed?Show solution ↓

Width ≥ 2.4 / 1.2 = 2.0 µm

Note: or use parallel straps, and check the vias too: each via has its own current limit.

N8 · ANTENNA RATIOBEGINNERA gate has 0.05 µm² of gate area and is connected to 25 µm² of metal during a given etch step. The rule limit is 400. Is it a violation?Show solution ↓

Ratio = 25 / 0.05 = 500 > 400 → violation

Note: jump to a higher layer to shorten the lower segment, or add an antenna diode.

READ A QoR REPORT

Walk through a post-route QoR summary

"Here's where the block is after routing. What do you look at first?" is a classic senior question. This generic summary hides one root cause behind several symptoms.

Post-route QoR summary   Block: dsp_core   Scenarios: 6 (2 modes × 3 corners)

  Std-cell utilisation              71.8 %
  Global-route overflow  H / V      0.02 % / 0.41 %       (1)
  Setup  WNS / TNS / NVP            -38 ps / -1.92 ns / 214   (2)
         worst scenario             func_ss_0p72v_125c
  Hold   WNS / TNS / NVP            -21 ps / -0.36 ns / 57    (3)
         worst scenario             func_ff_0p88v_m40c
  Max-transition violations         1,284                     (4)
  Max-capacitance violations        96
  Clock skew (func, ss)             118 ps   target 60 ps    (5)
  DRC violations                    2,310  (1,870 shorts)     (6)
  Antenna violations                34                        (7)
  Static IR drop (worst)            41 mV  (5.1% of 0.80 V)   (8)
  EM violations                     0

Vertical overflow is twenty times horizontal. Something local is eating vertical tracks: a narrow channel, macro pins or dense cells.
Setup fails at the slow, hot corner on 214 endpoints. Check whether they share a region.
Hold fails at fast, cold. Fix only after setup is understood.
1,284 transition violations usually follow detours around congestion or weak drivers on long nets.
Skew is nearly double its target, which hurts both setup and hold.
1,870 of 2,310 DRCs are shorts: a congestion signature, not a rule-deck problem.
Antenna errors are routine: fix with layer jumps or diodes.
IR just over a 5% budget. Check dynamic IR and whether the hotspot overlaps the failing paths.

What would you fix first?

The vertical congestion. Shorts, transition violations and a good share of the setup failures are probably downstream of it. Locate the overflow region, check whether the failing endpoints and shorts cluster there, and fix it in placement or the floorplan (padding, a wider channel, a moved macro). Then rerun and see how many other problems disappear.

Are the setup failures real?

Partly, but many may be caused by the transition violations and the high skew. Fix the clock tree to its target and clean up transitions before using lower-V_T cells or upsizing, otherwise you'll spend power fixing symptoms.

When do you fix hold?

After setup is stable and the clock tree is final, because skew changes will change the hold picture. Add delay cells near capture flops and avoid putting them in the congested region.

Is 5.1% IR drop acceptable?

It depends on the budget and on whether STA already accounts for it. If the hotspot overlaps the failing setup paths, it's making them worse: strengthen the local grid or add decaps there. The ebook has full sections on debugging, IR drop and signoff readiness.

RAPID-FIRE ROUND

20 quick questions, one-line answers

Screening calls often open like this. Answer each in a few seconds, then tap to check.

Which file gives cell and macro abstracts?

LEF.

Which file gives cell timing and power?

Liberty (.lib).

Which file carries the timing constraints?

SDC.

Which is placed first, macros or standard cells?

Macros.

What is a halo?

A keep-out region around a macro.

Lowest-metal power connection to cells?

Follow-pin rails.

Does a slower clock fix hold?

No.

Positive skew helps which check?

Setup (and hurts hold).

Ideal or propagated clocks after CTS?

Propagated.

What does CPPR remove?

Pessimism on the common clock path.

Worst corner for setup, usually?

Slow process, low voltage (hot, or cold with temperature inversion).

Worst corner for hold, usually?

Fast process, high voltage, cold.

Opposite-direction aggressor switching does what to the victim?

Slows it down.

Main fix for dynamic IR hotspots?

Decap cells near the hotspot.

DRC checks layout against what?

Foundry design rules.

LVS compares layout against what?

The schematic or netlist.

Two quick antenna fixes?

Layer jumping and antenna diodes.

Why do clock nets use NDRs?

Lower resistance, less crosstalk and EM risk.

What is a metal-only ECO?

A fix using spare cells and metal changes, with base layers untouched.

What does SPEF contain?

Extracted parasitic resistance and capacitance.

Full 616-question Physical Design ebook (with answers) →ASIC design interview questions →STA interview questions →CMOS interview questions →DFT interview questions →Look up any term in the glossary →