Floorplan to sign-off — the questions that separate candidates who've read about PD from those who've actually closed a design.
300+ carefully curated questions with detailed explanations, in one downloadable ebook.
Physical Design interviews go deep on the stages between a synthesized netlist and manufacturable silicon: floorplanning, placement, clock tree synthesis, routing, and the sign-off checks that catch problems before tapeout.
Interviewers often probe judgment here — not just definitions, but how you'd actually debug a congestion or timing problem in a real design.
Setting up the chip's physical structure before detailed implementation.
Positioning standard cells to balance timing, congestion, and power.
Distributing the clock signal with minimal skew and latency.
Connecting placed cells with actual metal wires.
Making sure the physical implementation still meets timing.
Delivering clean power across the whole die.
The final gate before a design goes to fabrication.
Confirming the layout matches the design intent.
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