Synopsys builds EDA software used to design chips (synthesis, static timing, simulation, place-and-route, verification) and licenses silicon IP such as interface PHYs and processor cores. It hires R&D software engineers, applications engineers and IP design and verification engineers, with large teams in Bengaluru, Hyderabad and Noida.
The order and number of rounds vary. Campus drives are usually shorter, while experienced-hire loops add rounds with more senior engineers.
Commonly aptitude plus either programming (for R&D roles) or digital/VLSI fundamentals (for AE and IP roles).
For R&D: data structures, algorithms and C++. For AE/IP: digital design, the ASIC flow, and HDL.
How EDA tools work inside (algorithms behind STA, synthesis and routing), or deep IP design/DV for IP roles.
For applications engineers: explaining a technical issue clearly, and debugging a customer's problem live.
Discussion and logistics.
Every company asks about fundamentals. These are the areas candidates report Synopsys pushing on hardest, given what the company builds.
Graphs, trees, dynamic programming. EDA is built on graph algorithms (timing graphs, routing).
Synthesis → PnR → STA → sign-off: what each step does and what can go wrong.
Timing graphs, arrival and required times, and how a tool computes slack.
TCL, the language EDA tools are driven with, plus Python for automation.
USB, PCIe, DDR and Ethernet concepts for interface-IP design and verification.
AEs are the bridge to customers, so clear explanations matter as much as depth.
Written by us to match the topics above, not copied from a real interview. Try answering out loud first, then open each one to see what the interviewer is really checking.
What they're probing: A DAG, a topological order, and longest-path propagation.
What they're probing: Translation, technology-independent optimization, technology mapping, and meeting constraints.
What they're probing: DFS with colours, and combinational loops.
What they're probing: Different parasitics, corners, OCV settings, or constraint mismatches.
What they're probing: Basic TCL fluency and familiarity with tool commands.
What they're probing: The analog/serial physical layer vs protocol logic, and the interface between them.
What they're probing: Better data structures, locality, incremental updates, and parallelism.
Where to apply: the official Synopsys careers site. Search for "ASIC", "design verification", "physical design" or "silicon" roles. For the wider market, see our company directory and fresher job guide. For typical pay, see the salary guides.
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