Revision notes: one concept per note

Combinational vs sequential logic

Combinational logic has no memory: the same inputs always give the same outputs, so it can be written as a truth table with no time column. Sequential logic stores state in latches or flip-flops, so what happened before changes the answer.

Real designs are islands of combinational logic sitting between registers. The registers decide when a value is held, and the logic decides what it becomes.

Latches, flip-flops and the edge

A latch is transparent while its enable is active, so its output can change many times per cycle. A flip-flop only samples at a clock edge. A standard flip-flop is two latches in series on opposite clock phases (master and slave).

Synthesized designs use flip-flops almost everywhere, because edge-triggering makes timing analysis simple and predictable.

Metastability in one picture

Think of a ball balanced on a hilltop between two valleys (0 and 1). If data changes inside a flop's setup/hold window, the ball can land on the top and wobble before falling either way, and how long it wobbles is unpredictable.

A synchronizer gives it extra time to fall before anyone looks. Each extra flop multiplies the safety margin, which is why the effect is exponential.

Number systems that show up in interviews

• Two's complement: invert and add 1. An n-bit range is −2ⁿ⁻¹ to 2ⁿ⁻¹−1.
• Gray code: g = b ^ (b >> 1). One bit changes per step.
• One-hot: exactly one bit set. Fast to decode, costs one flop per state.
• BCD: each decimal digit in 4 bits, used in displays.

Blocking vs non-blocking, the rule and the reason

The rule: <= in clocked blocks, = in combinational blocks, and never both in the same block.

The reason: non-blocking samples every right-hand side first and updates all targets together, which is exactly what a bank of flip-flops does at a clock edge. Blocking executes in order, like software, which matches how combinational logic settles.

The synthesis flow

Synthesis happens in stages: elaboration (parse the RTL and build a generic netlist), technology-independent optimization (Boolean simplification, constant propagation), then technology mapping onto real library cells under your SDC constraints. After that comes timing-driven optimization: upsizing on critical paths and downsizing elsewhere.

What you write matters. Synthesis optimizes structure, but it can't invent a better architecture.

Reset: which kind and why

An asynchronous reset works without a clock, but its release must be synchronized. A synchronous reset is timed like data, but needs a running clock. Most teams use asynchronous assertion with synchronous de-assertion, through one reset synchronizer per clock domain.

Also ask whether a flop needs reset at all. Datapath flops that are always written before being read often don't, which saves area and routing.

FSM coding in three blocks

A clean FSM has a state register (clocked), next-state logic (combinational, with a default), and output logic (from the state for Moore, or state and inputs for Mealy). Use an enum or named localparam values so waveforms show names, not numbers.

Registered outputs (or Moore outputs) are glitch-free. Mealy outputs react a cycle sooner but can pass input glitches through.

Verification methods compared

Code coverage vs functional coverage

Code coverage is automatic: which lines, branches, conditions and toggles were exercised. Functional coverage is written by you: which features and scenarios from the spec actually occurred.

100% code coverage can still miss a spec feature that has no code at all (a missing feature). High functional coverage with low code coverage points to dead or untested code.

Setup and hold as a budget

Think of one clock period as a budget. Clock-to-Q, the logic delay and the setup time must all fit inside it, adjusted by skew. That's the setup check. Hold is different: it checks that new data doesn't arrive so fast that it corrupts the value the capture flop is still holding, so the clock period never appears in it.

Slack, and reading a timing report

Slack = required time − arrival time. A timing report lists the path from start point to end point, cell by cell, with the delay each adds, then the required time from the clock side. Read it bottom-up: see the slack, then find which cells or nets eat the most delay.

Big delay on one net often means a long wire or high fanout. Many small delays mean too many logic levels.

The PnR flow in one line each

• Floorplan: where the big things go.
• Power plan: how current reaches every cell.
• Placement: where every cell goes.
• CTS: how the clock reaches every flop at the same time.
• Routing: the actual wires.
• Sign-off: proving it all works and can be manufactured.

ASIC sign-off, briefly

Sign-off means the design passes timing in every mode and corner, physical verification (DRC, LVS, antenna, density), power integrity (IR drop, EM), and formal equivalence against the RTL. Any exception needs a documented waiver, often agreed with the foundry.

The hidden skill is correlation: implementation tools and sign-off tools must agree, or you get surprises in the final week.

Why DFT exists

Fabrication creates random defects. Every chip must be tested in seconds on expensive equipment, but a deep internal flop can be almost impossible to reach from the pins. Scan chains turn every flop into a shift register in test mode, so a tester can load any state, run one clock, and read every result.

Power domains and low-power design

Dynamic power is α·C·V²·f, and leakage flows whenever a transistor is powered. The main techniques follow directly from that:

• Clock gating stops switching (cuts α), and the state is kept.
• Power gating cuts the supply (cuts leakage), and the state is lost unless retention flops are used.
• Multi-voltage and DVFS lower V (and f) where performance isn't needed.
• Multi-Vt cells use slow, low-leakage cells off the critical path.

Each technique adds verification work: isolation, level shifters, and power-state sequencing described in UPF.

Semiconductor fabrication, briefly

A fab builds chips on a silicon wafer layer by layer: lithography prints each layer's pattern using light through a mask, etching removes material where it isn't wanted, deposition adds new material, doping sets the electrical properties, and CMP polishes each layer flat. The transistors are built first (front end of line), then many metal wiring layers are stacked on top (back end of line).

Finished wafers are tested, diced into individual dies, packaged, and tested again.

Why yield drives cost

Defects land randomly across a wafer. A bigger die has a higher chance of catching one, so the fraction of good dies (the yield) falls as die area grows. Cost per good chip therefore rises much faster than die area. That's one reason large designs are increasingly split into chiplets: several small dies with high yield, packaged together.