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Combinational logic's output depends only on current inputs — no memory, no clock. Sequential logic's output depends on current inputs and past state, stored in flip-flops or latches. The practical tell: if you can draw it as a truth table with no time dimension, it's combinational; if "what happened before" changes the answer, it's sequential. Most real designs are sequential logic built from combinational blocks connected through registers.
Synthesis converts RTL into a gate-level netlist in two conceptual stages: a technology-independent stage (generic Boolean optimization) and a technology-mapped stage (mapping to actual standard cells from a specific library, honoring timing constraints from your SDC file). The synthesis tool tries to meet your timing constraints by picking faster (larger, higher-power) or smaller (slower, lower-power) cell variants along the critical path.
Modern chips split into multiple power domains that can be independently powered down or scaled in voltage to save energy when a block isn't needed. Key techniques: clock gating (stop toggling, keep state), power gating (cut power entirely, lose state), and multi-voltage design (run non-critical blocks at lower voltage). Each adds verification complexity — you now have to prove correctness across power state transitions, not just logic states.
Directed testing writes a specific test for a specific scenario — thorough but doesn't scale to complex designs. Constrained-random generates randomized-but-valid stimulus automatically, covering far more scenarios, checked against coverage goals. Formal verification mathematically proves properties hold for all possible inputs, no simulation needed — powerful for control logic, impractical for large datapaths. Most real verification plans combine all three.
Sign-off is the set of checks a design must pass before tape-out: timing (STA across all corners), power (IR drop, electromigration), physical (DRC — does the layout obey fab rules; LVS — does the layout match the schematic), and reliability (ERC, antenna checks). Failing any one of these after tape-out means an expensive re-spin, which is why sign-off is treated as a hard gate, not a formality.
Fabrication turns a design into physical silicon through repeated cycles of deposition, photolithography (patterning), etching, and doping — building up transistors and interconnect layer by layer on a wafer. Advanced nodes (below ~20nm) rely on FinFET or GAA transistor structures instead of traditional planar transistors to keep controlling leakage current as devices shrink.
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