Intel designs x86 CPUs, client and server SoCs, networking silicon and FPGAs (through Altera), and runs its own fabs and a foundry business. Its large India design centres in Bengaluru and Hyderabad work across design, verification, physical design, DFT and validation.
The order and number of rounds vary. Campus drives are usually shorter, while experienced-hire loops add rounds with more senior engineers.
Campus drives often start with an online test: aptitude plus digital electronics, computer architecture and C basics. Experienced hires usually start with a recruiter call.
Digital design from first principles: combinational/sequential logic, FSMs, timing basics, and a short Verilog or SystemVerilog exercise.
Deeper questions in your target area (DV, RTL, PD, DFT or validation), usually built around the projects on your resume.
An open-ended debug or design scenario, how you work with a team, and why this group.
Background, expectations, notice period and logistics.
Every company asks about fundamentals. These are the areas candidates report Intel pushing on hardest, given what the company builds.
Pipelines, hazards, caches, coherence basics. Expect more of this than at most other companies, given the CPU focus.
K-maps, flip-flops vs latches, setup/hold, metastability and synchronizers.
SystemVerilog OOP, constrained-random, coverage, assertions, and UVM for experienced roles.
Clock gating, power gating, multi-voltage domains and UPF awareness for design and PD roles.
Many Intel roles are validation: debugging real silicon on a lab setup with scripting (Python).
Every line is fair game. Be ready to draw your project's block diagram from memory.
Written by us to match the topics above, not copied from a real interview. Try answering out loud first, then open each one to see what the interviewer is really checking.
What they're probing: Probing whether you understand load-use hazards and why a stall (bubble) is still needed.
What they're probing: Trade-offs in memory traffic, consistency and complexity, not just definitions.
What they're probing: Clean state encoding, the overlapping case, and Mealy vs Moore choices.
What they're probing: Resolution time, clock frequency, data rate and the flop's characteristics.
What they're probing: Analysing coverage holes, reachable vs unreachable bins, and directed tests vs tuning constraints.
What they're probing: Glitches, and why a latch-based integrated clock gating (ICG) cell is used.
What they're probing: A structured approach: reproduce, isolate the corner, suspect timing paths, use the scan/debug infrastructure.
Where to apply: the official Intel careers site. Search for "ASIC", "design verification", "physical design" or "silicon" roles. For the wider market, see our company directory and fresher job guide. For typical pay, see the salary guides.
Real, recent interview experiences are the most useful prep there is. Send us your rounds and the questions you remember. With your permission we'll add them to this page anonymously, after checking them.