A one-page quick reference for the RTL concepts that come up constantly — FSM styles, blocking vs. non-blocking rules, CDC basics, and common pitfalls.
A printable, single-page version of this reference.
Use = (blocking) for combinational logic, <= (non-blocking) for sequential logic. Never mix both in the same always block.
Moore: output depends only on current state (more stable, one cycle slower). Mealy: output depends on state + input (faster reaction, can glitch).
Prefer synchronous reset for portability across technologies; use asynchronous reset only when a specification requires immediate response independent of the clock.
For single-bit signals crossing clock domains, use a two-flop synchronizer at minimum. For multi-bit buses, use a handshake or a FIFO — never synchronize a bus bit-by-bit.
In combinational always blocks, assign every output in every branch (including a default/else case) to avoid inferred latches.
Incomplete sensitivity lists, mixed blocking/non-blocking assignments, multiple drivers on a signal, and un-synchronized asynchronous resets are the most common bugs interviewers probe for.
This cheat sheet covers the basics — our RTL Design ebook goes much deeper.
See RTL Design questions